Subject: RE: Attributes and constant expressions
From: Michael McNamara (mac@verisity.com)
Date: Thu Oct 25 2001 - 08:20:43 PDT
J. Bhasker writes:
> Precedence: bulk
>
> Mac:
>
> But 'ah', there was no 'ifndef in Verilog in the '90s (Verilog 93).
> I think this time around, we should do it right, at least as part
> of the synthesis standard. We shall discuss this at the next
> Synthesis WG mtg. Thanks for raising this issue.
>
> - bhasker
Indeed; yet there was `ifdef
I look forward to the discussion.
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