Subject: Re: 1364.1 ballot responses
From: Steve Golson (sgolson@trilobyte.com)
Date: Thu Aug 29 2002 - 10:40:10 PDT
Shalom Bresticker wrote:
>
> I hope the following comments are constructive.
>
> SG05-06:
> Clarification:
> 6.1.4(a,h): The author stated that "current synthesis tools apply this to an entire module."
> I believe that statement was incorrect, and the draft is consistent with current use.
> The addition, on the other hand, is a substantive change to the draft, which requires reballoting.
I disagree.
Current synthesis tools do apply this directive to the entire module.
In fact, Synopsys Design Compiler has two different directives. Here's a
snippet from the HDL Compiler manual:
async_set_reset
When a signal has this directive set to true, HDL Compiler
searches for a branch that uses the signal as a condition.
HDL Compiler then checks whether the branch contains an
assignment to a constant value. If the branch does, the signal
becomes an asynchronous reset or set.
Attach this directive to single-bit signals, using the following
syntax:
// synopsys async_set_reset "signal_name_list"
async_set_reset_local
HDL Compiler treats listed signals in the specified block as if they
have the async_set_reset directive set to true.
Attach this directive to a block label, using the following syntax:
/* synopsys async_set_reset_local block_label "signal_name_list" */
The PRESTO Verilog Compiler manual has similar wording.
So it seems reasonable to use the attribute syntax to selectively apply
"async_set_reset" to either a module or a block, as needed. The same
goes for the "sync_set_reset" attribute.
I do not see this as a substantive change to the draft.
-seg
Steve Golson / Trilobyte Systems / +1.978.369.9669 / sgolson@trilobyte.com
Consulting in: Verilog, Synopsys, patent analysis, reverse engineering
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