Re: Implicit FSMs style with mutiple clocks

Subject: Re: Implicit FSMs style with mutiple clocks
From: VhdlCohen@aol.com
Date: Fri Dec 14 2001 - 23:31:11 PST

Attached is a copy of an implicit FSM in verilog and Synplify Pro results.
// Fetch data from memory, add data to reg[id], store sum to memory
// and register file
// 1. data_r <= mem[addr]
// 2. sum <= data + regfile[id]
// 3. mem[addr] <= sum; regfile[id] <= sum
Object of this exercise is to demonstrate the concepts only, not BEST
methodology.
Ben Cohen

<Jonas, Vinaya, Group,
    Your suggestion is much better than the UartTx example that we
have. Does anyone have an example of something like this that is
simple enough and short enough that we can use for the paper and
perhaps the standard? Ok even if it is not simple or short, I would
be interested.

Thanks,
Jim>

Jonas Nilsson wrote:
>
> I agree with Vinaya.
>
> The great thing with an implicit FSM is that the control is embedded
> into the dataflow description, which in many cases can make the code
> much more readable.
>
> It's even possible to mix the two, embedding local "implicit" state
> into the explicit states in an ordinary FSM, to describe mutlicycle
> operations in an ordinary FSM. This works fine in synthesis tools too.
>
> Implicit FSMs are great for some purposes, but they should of course
> not be used in cases where a "normal" explicit FSM would be better.
>
> Regards,
> Jonas Nilsson
>
> Vinaya Singh wrote:
> > I agree that implicit FSM is not a great way to write a controller.
If you have
> > state transition diagram, the best way to code is explicit machine.
> >
> > However, 'implicit FSM' is great way to model, multi-cycle
data-paths,
> > DSP algorithms etc. That is the data path devices, where control is
implicit and
> > embedded into it.
> >
> > Any voice from design community on this.
>
> --
> Jonas Nilsson, HARDI Electronics AB
> Derbyvagen 6B, SE-212 35 MALMO, SWEDEN
> Phone: +46-40-59 29 00
> Fax: +46-40-59 29 01
> E-mail: jonas@hardi.se
> WWW: http://www.hardi.se 

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis                        
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL training with a focus on hardware design and test.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

----------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/>                 vhdlcohen@aol.com  
Author of following textbooks: 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 
0-9705394-2-8 
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Fri Dec 14 2001 - 23:43:43 PST