// rtl_synthesis off/on
On the vhdl front, people have been asking to have the ifdef directive
in VHDL so that pragmas in comment form can be avoided.
The Verilog language already provides a nice mechanism for conditional
compilation. Why not use this? The biggest advantage is the fact the both
synthesis (will) and simulation tools understand this directive and hence
the potential problem of simulation mismatch (occurs often when pragmas
in comment form are used) is avoided.
I propose we drop the conditional compilation pragma and support the ifdef
verilog compiler directive.
I know this is going against the defacto std, but avoiding simulation mismatch
is a big gain ....
- bhasker
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Date: Sun, 5 Jul 1998 12:56:44 -0700
From: owner-vlog-synth@vhdl.org (Michael McNamara)
Orig-From: Michael McNamara <mac@surefirev.com>
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To: "Smith, Douglas J" <djsmith@ingr.com>
Cc: vlog-synth@eda.org
Subject: pragmas
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Smith, Douglas J writes:
> All,
>
> At the recent face-to-face meeting we discussed pragmas.
I apologize for missing the face to face, and would like to
know when the next is planned.
> One of the issues was a means of communicating to a synthesis tool
> that it should map directly to a multiplexer. As such I have am
> proposing
>
> // rtl_map_to_mux
>
> which can be associated with a case or if statement.
> The problem I see with this is that it could excalate, for example,
> why not hae a pragma for mapping onto a counter.
> Please send in and feedback. When I send out email to this reflector
> I will include at the bottom a full list of proposed prgmas as they
> exist at that point in time. Currently this is as follows.
>
> Doug Smith
>
>
> Verilog IEEE 1364.1 - proposed pragmas
> ======================================
>
> The following pragmas are being proposed for the standard:
>
> 1. Conditional compilation pragmas
>
> // rtl_synthesis off
> // rtl_synthesis on
>
> 2. Case decoding pragmas
>
> // rtl_full_case
> // communicates to the synthesis tool case choices are exhaustive.
>
> // rtl_parallel_case
> // communicates to the synthesis tool case choices are mutually
> exclusive.
>
> 3. Mapping to a multiplexer
>
> // map_to_mux
> // communicates to the synthesis tool to map directly to a
> multiplexer
> // and shall apply to case and if statements.
I'd like to suggest we really introduce pragmas, instead of
"stealing" from the user's 'comment name space'
I totally understand the seductive beauty of adding what
appears to be a comment to a line of code, and have every other tool
ignore the thing, except yours. However, every other tool might not.
I also agree that we can not continue with
// synopsys translate_off
as it enshrines the defacto standard a bit much. I believe also that
pragmas are not just for synthesis -- the simulator could profit from
the same design information.
Therefore I'd like to propose that pragmas be introduced by a
common verb. Something like:
// pragma rtl_translate_off
// pragma rtl_full_case
and so on. Users do have comments that look like map_to_mux!
-mac
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