Subject: Re: 6.1 Synthesis attributes // minor syntax update
From: Daryl Stewart (Daryl.Stewart@cl.cam.ac.uk)
Date: Wed Apr 03 2002 - 03:50:37 PST
> 6.1 Synthesis attributes
> Change from:
> (* synthesis, <attribute=value_or_optional_value> *)
>
> TO:
> (* synthesis, {<attribute=value_or_optional_value>,
> <attribute=value_or_optional_value>}*)
That's "synthesis followed by zero or an even number of alternately
comma-separated attributes"
(* synthesis, a=1, b=1 c=1, d=1 e=1, f=1 ... *)
Don't you mean
(* synthesis, <attribute=value_or_optional_value>
{, <attribute=value_or_optional_value> } *)
ie "comma-separated list of synthesis followed by one or more attributes"
cheers
Daryl
Compile Verilog to C at www.tenisontech.com
This archive was generated by hypermail 2b28 : Wed Apr 03 2002 - 04:00:41 PST