Subject: 1364.1 v2.1 draft COMMENTS
From: VhdlCohen@aol.com
Date: Fri Mar 29 2002 - 14:52:51 PST
Am having an issue with the "note" page 15
5.7 Modeling random access memories (RAM)
NOTE--If combinational logic is desired instead of a RAM,use the attribute
logic_block instead of the attribute
ram_block.
How about something like:
NOTE--If latch or register logic is desired instead of a RAM,use the
attribute logic_block instead of the attribute
ram_block.
-----
Page 21, keep
If a reg has a keep attribute and an fsm_state attribute,the fsm_state
attribute shall be ignored.
This attribute does not apply if the reg has not been inferred as an
edge-sensitive storage device.
The above 2 separate statements in two separate paragrahs should be in one
paragraph because the 2nd line refers to the first statement
(...fsm_state...). Otherwise, I don't understand it. Change to:
If a reg has a keep attribute and an fsm_state attribute,the fsm_state
attribute shall be ignored. This attribute does not apply if the reg, with
the fsm_state attribute, has not been inferred as an edge-sensitive storage
device.
---- Page 23 h)(*synthesis,sync_set_reset ="signal_name1,signal_name2,..."*) The presence of the attribute shall cause the set/reset logic to be applied directly to the set/reset terminals of an edge-sensitive storage device if such a device is available in the technology library. Can that cause a simulation mismatch since rst will be asynchronous, but FF does not have the asynchronous style. ?? --- A.7 Specify section, page 76 Is "specify" supported? Timing check supported? Why is A.7 there? ??? -------------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 <A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------
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