Subject: Re: 1364.1 pragmas
From: John Michael Williams (jwill@AstraGate.net)
Date: Thu Aug 29 2002 - 07:47:57 PDT
Hi Cliff.
Clifford E. Cummings wrote:
>
> At 04:21 PM 8/28/02 -0700, you wrote:
> ... My take on attributes from Verilog-2001
> days was that we were trying to get vendors away from parsing comments (
> //synopsys full_case) and provide a mechanism to make Verilog source code
> useful to tools other than just simulators (or synthesis tools).
> ...
WHY are you "trying to get vendors away from parsing comments?"
Comments are the only syntactic commonality guaranteed to
be shared among all simulation or synthesis tools, including
Verilog, VHDL, SystemC, C, and even Pascal. Actually,
the 1364.1 attribute construct is in the form of
a Pascal comment!
By embedding synthesis directives in comments, the
directives, if nothing else, are totally portable.
By being strict about the exact format of an
embedded directive, accidental reading of a real
comment as a directive can be minimized.
I'm not saying the goal of shifting synthesis
directives to language-specific constructs is wrong,
but I don't see any good reason for it, and there seems
to be at least one serious disadvantage (nonportability).
--
John
jwill@AstraGate.net
John Michael Williams
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