Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
From: VhdlCohen@aol.com
Date: Thu Dec 13 2001 - 14:22:55 PST
I believe that Synopsys behavioral compiler does support it. In any case,
there are lots of things that our spec provides that Synopsys does support
(e.g., ROM init with files).
Ben
In a message dated 12/12/01 11:20:39 PM Pacific Standard Time,
Shalom.Bresticker@motorola.com writes:
> But Synopsys Design Compiler does not support it, to the best of my
> knowledge. Shalom
> VhdlCohen@aol.com wrote:
> >> By the way, Synplify also synthesizes that code. Attached is a PDF of
>> the code and result. And that brings an interesting question: Do we want
>> to include the support of Implicit FSMs style with mutiple clocks? I read
>> Cliff's answer, and he has good points, but the tools seem to support
>> this style. In other words, if vendors support the multiple clocks in a
>> block, do we really want to say "NO, we won't let you do that". I
>> thought our job is not necessarily to teach good style, but rather define
>> templates and attributes for use in interroperability. From our spec "1.1
>> Scope
>> This standard defines a set of modeling rules for writing Verilog HDL
>> descriptions". These are not guidelines on how to do design.
>> Comments?
>> Ben Cohen
>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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