Subject: Here we go again ...
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Tue Sep 26 2000 - 06:18:16 PDT
Dear WG member:
As Verilog-2000 is in its final stages, it is time to restart our activities
in this synthesis WG. Work in this WG had momentarily stopped since July 99
pending Verilog-2000 standardization - some WG members felt that it was
better to incorporate the Verilog-2000 synthesizable features into the
synthesis standard, rather than have one synthesis standard appear in 1999
and have a new version of Verilog succeed soon after.
We will start the WG meetings by discussing synthesizablity features of
the Verilog-2000 language. Please spend some time reviewing the Verilog-2000
LRM, especially the new sections. You may also look at a paper by
Stuart Sutherland at this years HDLCon conference for what new features are
getting into the language. His presentation is online at
http://www.sutherland-hdl.com/verilog-2000_presentation.pdf.
I will be posting a list of new features and its applicability for synthesis
shortly - we can use this as a start for our discussions. I plan to hold
a telecon WG meeting once every 4-6 weeks (with some face-to-face meetings).
Regards,
- J. Bhasker, Cadence Design Systems, 610-398-6312, jbhasker@cadence.com
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
This archive was generated by hypermail 2b28 : Tue Sep 26 2000 - 06:23:44 PDT