Inferring ROMs in Verilog

Subject: Inferring ROMs in Verilog
From: VhdlCohen@aol.com
Date: Fri Jun 22 2001 - 09:24:23 PDT

ref: IEEE P1364.1 / D1.6, Draft Standard for Verilog® Register Transfer Level
Synthesis
The document DOES NOT specify HOW ROM are inferred, and which attributes if
any can be used to infer ROMs.
Below is information from Synplify help file that addresses this issue. I
recommend that we add a recommendation and possibly attributes to infer ROMs. 

---
//from Synplify help 3/13/01
"Generally, Synplify infers ROMs from HDL source code that uses CASE 
statements, or equivalent IF statements, to make 16 or more signal 
assignments using constant values (words). The constants must all be the same 
width.

Verilog Example:
module rom2(z, a);
output [3:0] z;
input [4:0] a;
reg [3:0] z ;
always @(a)
begin
    case (a)
        5'b00000: z = 4'b1011;
        5'b00001: z = 4'b0001;
        5'b00100: z = 4'b0011;
        5'b00110: z = 4'b0010;
        5'b00111: z = 4'b1110;
        5'b01001: z = 4'b0111;
        5'b01010: z = 4'b0101;
        5'b01101: z = 4'b0100;
        5'b10000: z = 4'b1100;
        5'b10001: z = 4'b1101;
        5'b10010: z = 4'b1111;
        5'b10011: z = 4'b1110;
        5'b11000: z = 4'b1010;
        5'b11010: z = 4'b1011;
        5'b11110: z = 4'b1001;
        5'b11111: z = 4'b1000;
        default: z = 4'b0000;
    endcase
end
endmodule

...
Attribute; Altera (APEX, ACEX families and FLEX10K). You can describe a ROM 
structure in RTL code using a CASE statement. By applying the syn_romstyle 
attribute to the signal output value, you can control if the ROM structure is 
implemented as discrete logic or as an ESB block for APEX or EAB blocks for 
FLEX and ACEX.
By default, Synplify and Synplify Pro implement small ROMs (less than seven 
address bits) as logic, and large ROMs (seven or more address bits) as ESBs 
for APEX and EABs for FLEX and ACEX.

You can globally disable automatic use of ESBs/EABs for inferred ROMs by 
setting altera_auto_use_eab = 0 (FLEX and ACEX) or altera_auto_use_esb = 0 
(APEX).
Setting syn_romstyle=logic in an APEX, ACEX, or FLEX device forces an 
implementation using discrete logic primitives. Setting 
syn_romstyle=block_rom forces an ESB implementation when targeting APEX 
devices, and an EAB implementation when targeting FLEX and ACEX devices.

.sdc File Syntax and Example

define_attribute {rom_primitive} syn_romstyle {logic|block_rom}

For example:

define_attribute {z_20[3:0]} syn_romstyle {block_rom}

Verilog Syntax and Example

object /* synthesis syn_romstyle = "logic|block_rom" */ ;

The following example shows you how to use the syn_romstyle attribute to 
implement a ROM structure as block_rom, which forces an ESB/EAB 
implementation.

reg [3:0] z /* synthesis syn_romstyle = "block_rom" */;

The following example shows you how to use the syn_romstyle attribute to 
implement a ROM structure as logic, which forces an implementation using 
discrete logic primitives.

reg [8:0] z /* synthesis syn_romstyle = "logic" */;

..
nferring ROMs Examples

The following examples show you how to infer a ROM.

Verilog Example

/* Sparsely populated ROM */
module rom2(z, a);
output [3:0] z;
input [4:0] a;
reg [3:0] z /* synthesis syn_romstyle = "block_rom" */;
always @(a) begin
    case (a)
        5'b00000: z = 4'b1011;
        5'b00001: z = 4'b0001;
        5'b00100: z = 4'b0011;
        5'b00110: z = 4'b0010;
        5'b00111: z = 4'b1110;
        5'b01001: z = 4'b0111;
        5'b01010: z = 4'b0101;
        5'b01101: z = 4'b0100;
        5'b10000: z = 4'b1100;
        5'b10001: z = 4'b1101;
        5'b10010: z = 4'b1111;
        5'b10011: z = 4'b1110;
        5'b11000: z = 4'b1010;
        5'b11010: z = 4'b1011;
        5'b11110: z = 4'b1001;
        5'b11111: z = 4'b1000;
        default: z = 4'b0000;
    endcase
end
endmodule

 

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Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
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* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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