KenCoffman: (he is the task leader for the semantics part section 4)
I think we need to add a stmt to the effect under 4.2.1. Such as:
Clock edge expressions (posedge and negedge Clock) shall not appear
in statements within an always statement.
They can only appear within the event list of the
always statement.
What do you think?
- bhasker
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Subject: Edge-sensitive sequential logic
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From: owner-vlog-synth@vhdl.org (Tommy Kelly)
Orig-From: Tommy Kelly <tommyk@mekb2.sps.mot.com>
Date: 26 Jun 1998 12:03:21 +0100
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Sections 4.2.1.1 and 4.2.1.2 in the draft refer to the
verilog syntax for representing edge-sensitive logic:
always @(posedge clock)
or always @(negedge clock)
and of course either can have an asynchronous reset
term (although the comment in the last part of the
example on page 13 says "synchronous reset" which
I think is wrong, no?).
But, during recent a discussion on comp.lang.verilog
it emerged that the Synplicity tool will synthesize
RTL where the @(posedge clock) is *within* the always
block. I've given the example at the end of this mail,
but my question is, "is this desirable?".
design_compiler from synopsys refuses to accept
such a construct, and because that is the only
tool I've used I've come to feel that @(posedge ...)
belongs only in the sensitivity list of an always
block. In that, both Synopsys and I seem to be in
agreement with the authors of the draft standard.
Thoughts?
regards,
Tommy
/* Here's the example */
module test(
reset, clock,
req1, req2,
ack1, ack2
);
input reset;
input clock;
output req1;
output req2;
input ack1;
input ack2;
reg req1;
reg req2;
reg [0:2] state;
`define DO_FIRST 3'b001
`define DO_SECOND 3'b010
`define IDLE 3'b100
always @(posedge clock)
begin
if (reset)
begin
req1=0;
req2=0;
end
else begin
case (state)
`DO_FIRST:
begin
handshake1;
state=`DO_SECOND;
end
`DO_SECOND:
begin
handshake2;
state=`IDLE;
end
`IDLE:
state=`DO_FIRST;
default:
state='bx;
endcase
end
end
task handshake1;
begin
req1=1;
while (ack1==0 && reset==0)
@(posedge clock);
req1=0;
while (ack1==1 && reset==0)
@(posedge clock);
end
endtask // handshake1
task handshake2;
begin
req2=1;
while (ack2==0 && reset==0)
@(posedge clock);
req2=0;
while (ack2==1 && reset==0)
@(posedge clock);
end
endtask // handshake2
endmodule // test
/* End of example */
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