Subject: RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Fri Feb 08 2002 - 13:37:50 PST
Here is one item that I missed from my earlier meeting minutes:
11. Stefan Boyd agreed to present a brief status of our WG at the forthcoming
HDLCON conference.
- bhasker
-----Original Message-----
From: Jayaram Bhasker
Sent: Friday, February 08, 2002 2:57 PM
To: vlog-synth@eda.org
Subject: RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8,
2002: MEETING MINUTES
Meeting minutes: Telecon Feb 8, 2002
Attendees:
Ben Cohen
Cliff Cummings
Joe Wetstein
Stefan Boyd
Mike McNamara
JenJen Tiao
J Bhasker
1. Cliff reported that the set of attributes that we currently have
is a good start for the standard. The one additional one that he would
like to see added was the "label" attribute. This attribute can be used to
label any item. The application of this label is not specified by the standard.
2. The draft is being updated to conform to the new IEEE-SA style. Draft 1.10
will be in the new format. It is not too different from the old one except that
the IEEE Frame templates and paragraph formats had to be used.
3. Forgot to mention this today: The draft with the new format changes is being
reviewed by IEEE for consistency.
4. Bhasker explained the IEEE process briefly. Most of the work will be done
electronically. The ballot invitation will be going out shortly. YOU MUST BE
AN IEEE-SA MEMBER TO PARTICIPATE IN THE BALLOT. If not, this is a good time to
become one.
5. Discussed the keep attribute. Agreed to keep only one form of keep: only the
specified object and its internals are not optimized away - everything around
it may be optimized away.
6. Ben proposed that attributes ought to have an on/off value, that is,a
mechanism to disable attributes by specifying a value of 0. So this was discussed
and agreed upon:
All attributes that can have an <optional_value> may have the value 0 to turn off/disable
its interpretation. No <optional_value> specified is same as enabling the attribute.
The optional_value can be any constant expression (including a string, which is treated
as a non-zero value). Allowing a constant expression as a value will allow use of
parameters in the expression.
7. Draft 1.10 will be updated to include the fsm_encoding attribute.
8. The next WG meeting is expected to be a face-to-face meeting during the HDLCON
conference. Alternately, we may have a telecon on March 8.
9. Cliff to provide additional material for the Annex by the next WG meeting date.
10. Draft 1.10 will be posted by end of next week. Please review and post feedback.
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: Jayaram Bhasker Sent: Monday, February 04, 2002 2:13 PM To: vlog-synth@eda.org Subject: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002
The next Verilog RTL Synthesis Interoperability WG teleconference is scheduled for FEB 8, 2002 from 12:00pm to 1:30pm.
Here are the call details:
CALL DATE: FEB-08-2002 (Friday) CALL TIME: 12:00 PM EASTERN TIME DURATION: 1 hr 30 min USA Toll Free Number: 888-469-3061 USA Toll Number: +1-712-271-3820 PASSCODE: 39333 LEADER: Mr Jayaram Bhasker
Agenda:
1. Cliff to present additional attributes. 2. Bhasker - IEEE new template for draft/standard. 3. Bhasker - brief overview of standardization process. 4. Any draft review comments for discussion.
The WG meeting in March is likely to be a face-to-face meeting during HDLCON in Santa Clara (Mar 11-12) - more details later.
Regards,
- J. Bhasker, Cadence Design Systems, 610-398-6312, jbhasker@cadence.com Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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