vlog 2000 feature list


Subject: vlog 2000 feature list
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Fri Jul 06 2001 - 12:57:21 PDT


As requested in todays WG meeting, I am posting the vlog 2000 feature list for
which I am looking for volunteers to help review.

If you are interested in help review, select from the items marked with "Open".
If you do not have the Verilog2K LRM, I will send you the
relevant hard copy pages of the
features that you have selected for review.

- bhasker

J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
610.398.6312, 610.530.7985 (fax), jbhasker@cadence.com

This document lists the new Verilog 2001 features and
suggests to its synthesizability:

FEATURE SYNTHESIZABLE? OWNER
------- -------------- -----

 1. Generate block (for, ifelse, case) Yes Bhasker

 2. Multidimensional arrays Yes Bhasker

 3. Bit and part-select with arrays Yes Bhasker

 4. Enhanced file I/O No Bhasker

 5. Re-entrant tasks and functions Yes; recursion with static bnd
                                                                PraveenTiwari

 6. Configuration block Yes StephenBoyd

 7. Library map files Yes StephenBoyd

 8. Named parameter association Yes Open

 9. Comma sep sensitivity list Yes CliffCummings

10. Event symbol @* Yes CliffCummings

11. ANSI style I/O decls Yes Open

12. Automatic width extension beyond 32 bits Yes Open

13. Indexed part select Yes PraveenTiwari

14. Reg initial declaration No Open

15. Signed type Yes MuzaffarKal

16. System functions $signed, $unsigned Yes Open

17. Constant functions Yes Open

18. Addtl cond compilation(`ifndef,`elsif,`undef) Yes Open

19. Power op (**) Yes - first operand is 2, or
                                                opds are constants.
                                                                Open

20. 'line compiler directive Yes (ignored) Open

21. Arithmetic shift ops (<<<, >>>) Yes JoeWetstein

22. Combined port and data type decl Yes Open

23. Parallel case attribute Yes JoeWetstein
    (* rtl_synthesis_parallel_case *)

24. Full case attribute Yes JoeWetstein
    (* rtl_synthesis_full_case *)

25. On-detect pulse error propogation No Open
    (pulsestyle_onevent, pulsestyle_ondetect)

26. Negative pulse detection No Open
    (showcancelled, noshowcancelled)

27. New timing checks No Open
    ($removal, $recrem, $timeskew, $fullskew)

28. Negative timing constraint No Open
    (modified $setuphold)

29. New VCD system tasks No Open

------------------------
   
- J. Bhasker, Last updated: July 6, 2001



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