Hi:
This is a reminder of our upcoming PAR1364.1 Working Group meeting.
For directions to Mentor Graphics, where the meeting will be held,
visit: http://192.94.39.7/cet/CTR_SJC.html
A draft is available on the home page, http://www.eda.org/vlog-synth. Please
bring a copy with you to the meeting. (No hard copies may be available at
the meeting).
One of the important items to be discussed at the meeting is that of
identifying task leaders. If you are not able to make it to the
WG meeting and if you are interested in being a task leader, please send
me email by June 10. Task leaders are required for:
1. Semantics
2. Syntax
3. Compiler directives (pragmas)
See you all in San Jose.
- bhasker
----------
X-Sun-Data-Type: default
X-Sun-Data-Description: default
X-Sun-Data-Name: wg_meeting.txt
X-Sun-Charset: us-ascii
X-Sun-Content-Lines: 41
May 14, 1998
Dear Colleague:
I would like to invite you to the first face-to-face
meeting of the working group
developing IEEE PAR 1364.1, Draft Standard for Verilog Register Transfer
Level Synthesis. The scope of the project is :
"to develop a standard syntax and semantics for Verilog RTL
synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL)
which is suitable for RTL synthesis and shall define the semantics of
that subset for the synthesis domain. This standard shall be based
on the current existing standard IEEE 1364."
The meeting will be held at:
Mentor Graphics, Silicon Valley (address and directions will be send out later)
beginning at 1:00pm on Thursday, June 18, 1998. The meeting is expected to end
around 5:00pm.
The preliminary agenda is as follows:
a) Introductions
b) WG scope and purpose
c) WG policies
d) General issues on draft 1.0
e) Select task leaders
f) Future plan and meetings.
Should you have any questions, please contact me at your earliest convenience.
Sincerely,
- J. Bhasker, Lucent Technologies (610-712-3983, jbhasker@bell-labs.com )
Chair, IEEE 1364.1 Verilog RTL Synthesis Interoperability Working Group