Subject: correction to section 5.4
From: Muzaffer Kal (muzaffer@dspia.com)
Date: Thu Mar 28 2002 - 01:15:28 PST
hi,
the following is the code in section 5.4 example 18 :
------------------------------------------------------
module ztest (test2, test1, test3, ena);
input [0:1] ena;
input [7:0] test1, test3;
output [7:0] test2;
wire [7:0] test2;
assign test2 = (ena == 2’b01) ? test1 : 8’bz;
// test2 is three-state when ena is low.
assign test2 = (ena == 2’b10) ? 8’bz : test3;
// Both drivers to test2 have an assignment of z.
endmodule
------------------------------------------------------
As there is a conflict between two assignments when ena==2'b01,
(test2 is assigned both test1 and test3) the second assignment to test2
should read:
assign test2 = (ena == 2’b10) ? test3 : 8’bz;
so that ena selects test1 and test3 in a non-conflicting encoding.
Also the first comments should read:
// test2 is three-state when ena is not 2'b01
which obviously only applies to that assignment. The second assigment
makes test2 three-state when ena is not 2'b10 (with my correction) which is
to
say test2 is three-state when ena is 2'b00 or 2'b11.
regards,
Muzaffer Kal 408.654.9573
DSPIA Inc.
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm
implementations
This archive was generated by hypermail 2b28 : Thu Mar 28 2002 - 01:21:37 PST