Subject: Re: Suggestions for synthesis tools
From: John Michael Williams (jwill@AstraGate.net)
Date: Fri Oct 18 2002 - 20:33:06 PDT
Hi Ben.
We can't "force" vendors to do anything.
Standards adoption is strictly voluntary, and I
don't think standards development should support
the regulatory superstructure required to "force"
anyone to do anything.
I agree that EDA tools tend to be lower in quality
than commercial software such as MS Windows. But
consider that Windows has been in production since,
what, 1991? (That's what my Windows 3.1 copyright
notice implies). I am sure Windows 3.0 had its
flakey days . . ..
--
John
jwill@AstraGate.net
John Michael Williams
VhdlCohen@aol.com wrote:
>
> I had an interesting discussion with a NASA user about current
> restrictions of synthesis tools, and suggestions for uprades.
> Thought I would share this in the hope that vendors do
> something in that direction. It does not seem that this is
> something that we can put in our document, except for a pragma
> that prevents FF replication.
> Comments?
> -----
> Suggestions for your committee work:
>
> - Validation suite
> - Publish algorithms and control them
> - Force the vendors to have FSM's with no lock up. The
> way
> done by Synplicity is simply ridiculous and introduces
> new
> error modes with their poor design, modes hidden from
> the
> user and totally non-obvious.
> - Force the vendors to have flip-flop replication disabled
> by DEFAULT.
> - Force the vendors to actually listen to the directives
> in
> the code by DEFAULT. Currently, they only take the
> directives as a guide and then do what they want
> anyways,
> as they feel they are good hardware designers and we are
> not.
> - Force the vendors to publish on their www site a list of
> reported bugs and their fixes.
>
> I note that the HDL vendors are so desperate that you have
> to pay to be able to generate modules and not complete chips.
> Yes, it has more functions in the cheaper versions but you
> can't disable them. So, if you're a low cost user, it won't
> let you embed HDL code in a schematic unless you pay them not
> to put in the I/O modules. Why are they so scared? Why do
> they have to resort to Bill Gates style marketing tricks?
>
>
> ----------------------------------------------------------------------------
> Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
>
> http://www.vhdlcohen.com/ vhdlcohen@aol.com
> Author of following textbooks:
> * Real Chip Design and Verification Using Verilog and VHDL,
> 2002 isbn 0-9705394-2-8
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
> 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
> 0-7923-8115
> ------------------------------------------------------------------------------
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