`celldefine issue: Verilog RTL synthesis subset

Michael McNamara (mac@surefirev.com)
Sat, 27 Feb 1999 09:38:08 -0800 (PST)

Jayaram Bhasker writes:
> One issue identified at the last telecon was how to support `celldefine \
> `endcelldefine.
>
> Here are the various choices:
>
> A. Ignore these directives - in which case, user may have to put a rtl_synthesis
> on/off around the module that is enclosed by `celldefine.
>
> B. Issue error - User may have to put rtl_synthesis on/off around `celldefine
> \ `endcelldefine.
>
> C. Interpret `celldefine\`endcelldefine as rtl_synthesis off/on respectively.
>
> Please send in your feedback by Mar 6.
>
> - bhasker

If tools do not understand a directive, they should ignore the
directive.

This is easy to state, and given a concise description of a directive,
is easy to implement.

Verilog does not have a concise description of a directive; consider
`uselib, which really needs a BNF to parse its many optional
arguments.

Now, `celldefine .. `endcelldefine is one that happens to be easy to
parse, and ignore.

Typically, `celldefine means that the enclosed module (or modules!)
came from a library, or more precisely, are things that the pli
routine 'acc_next_cell' will iterate over. Most typically, this
routine is used by pli implemented delay calculators.

Pretty much every other user of such a module should just ignore the
`celldefine and `endcelldefine directives, which is like your option
A.

However, I'd like to propose an option A.1, which requires a sythesis
tool to have a list of recognized and ignored directives, which
include `celldefine, `endcelldefine, `accelerate, `noaccelerate,
`default_nettype, and many of the 3 dozen or so directives that
Verilog-XL supports.

We should ask Cadence to officially tell us the syntax and
documentation of these so that we can, on a case by case basis, decide
they should be ignored, or supported, or what ever else might be
appropriate.

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