Community Newsletter: August 2025

IN THIS ISSUE:

Message from the Chair
New Videos Available!
- View the updates to IEEE 1800.2 presented during DVCon U.S. 2025
- Portable Stimulus DVCon U.S. 2025 Workshop Video Now Available!
Upcoming Events
- DVCon Taiwan
- DVCon India
- DVCon Europe
- SystemC Evolution Day
Accellera-Sponsored Luncheon Focused on AI Draws a Crowd at the 62nd DAC
More Resources
- DVCon Archives – U.S. 2025 Program Now Available!
- Hundreds of Videos Available On-Demand
IEEE Get Program Update

Message from the Chair

Lu Dai, Accellera Systems Initiative Chair I hope you all have enjoyed the summer season. I am pleased to share some exciting updates as we move into the latter part of the year. First, please join me in welcoming Google, Samsung, and Ubilinx as the newest members of the Accellera community. Their participation will further strengthen our collective efforts to advance design and verification standards across the industry.

Our working groups are making significant strides. We anticipate the SystemC-AMS LRM will be complete and handed over to the IEEE by the end of the year. The Functional Safety, SystemC Synthesis and SystemVerilog-MSI working groups are also on track to release draft standards for public review by years end.

Our conferences continue to be places to gather, exchange new ideas, and connect with colleagues from across the industry. DVCon China and DVCon Japan recently had great participation from their local communities. Next month DVCon Taiwan and DVCon India will take the stage, followed in October by DVCon Europe and SystemC Evolution Day. With six conferences hosted each year around the world, there is always one within reach, making it easier than ever to join us for these informative and inspiring events.

Finally, I am happy to report that Accellera remains in excellent financial health. This year, we launched the Summer of Code program, engaging paid student interns to work on SystemC projects, and the results have been very encouraging. Building on this success, we’re exploring opportunities to expand the program by hiring more student interns to contribute to other standards, so stay tuned for more on this promising initiative.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

New Videos from DVCon U.S. 2025 Available!

Unlock the Latest in UVM & Simplify Migration to IEEE 1800.2

Discover the latest updates to the IEEE 1800.2 UVM standard in Accellera’s reference implementation (2020.3.1), introduced during a workshop at DVCon U.S. 2025. Learn how these enhancements improve performance, simplify migration from UVM 1.2, and address challenges faced in earlier transitions.

The session highlights backward compatibility, new community resources such as Accellera’s public GitHub repository, performance improvements, and functional enhancements that streamline verification workflows and reduce the need to maintain modified UVM libraries. It also looks ahead to future developments, including plans for updating the Register Abstraction Layer (RAL).

View the UVM workshop video on demand >

Portable Test and Stimulus Standard Matures and Looks to the Future

The Portable Stimulus Standard (PSS) has reached an important milestone with the release of version 3.0, further strengthening its role in modern verification methodologies. At DVCon U.S. 2025, the workshop “PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More”offered attendees a deep dive into the practical benefits of this evolving standard.

The session demonstrated how behavioral and data coverage can be combined to deliver a more complete measure of test effectiveness, ensuring that verification teams can capture both the scenarios exercised and the quality of the data applied. The workshop also highlighted the PSS Working Group’s development of a methodology library designed to simplify scenario creation, encourage reuse across tools and teams, and promote interoperability, a key factor for adoption across diverse design and verification flows.

In addition to exploring these new capabilities, the workshop provided a forward-looking perspective with a preview of planned features for PSS 3.1. Attendees gained insight into how the standard is continuing to evolve to meet industry needs and how upcoming enhancements will further support more efficient and automated verification practices.

View the Portable Stimulus workshop video on demand >

Upcoming Events

DVCon Taiwan

Now in its third year, DVCon Taiwan will take place on September 9, 2025, at the Hsinchu Lakeshore Hotel.

The day will begin with the keynote “A Global Journey in Design Verification: History, Challenges, and Outlook,” presented by Chinh Tran, Deputy General Manager at MediaTek. A second keynote, “Harnessing Agentic-AI to Accelerate Verification,” will be delivered by Matt Graham, Senior Group Director at Cadence, highlighting how agentic-AI and advanced engines can help verification teams overcome challenges and speed IP and SoC verification closure.

A panel discussion, “The Dawn of GenAI in Design and Verification,” will bring together experts from Cadence, ChipAgents, Fujitsu, MediaTek, Siemens EDA, and Synopsys to share perspectives on the transformative role of generative AI.

In the afternoon, attendees can look forward to a full slate of technical presentations, including a session led by Accellera’s Clock Domain Crossing Working Group.

For program details and registration information, visit the DVCon Taiwan 2025 conference website.

To view the archives from past DVCon Taiwan conferences, visit here.

DVCon India

Celebrating its 10th anniversary, DVCon India 2025 is centered around the theme, “Architecture to Analytics (A2A),” emphasizing the full-chip design and verification lifecycle. The conference includes a dynamic lineup of vision talks and keynote sessions from industry leaders, including:

Jean‑Marie Brunet, Vice President and General Manager, Hardware Assisted Verification, Siemens, will present the vision talk, “Software‑defined hardware design relies on AI and intelligent verification,” exploring how AI is transforming verification across analog/mixed-signal and RTL flows.
Dr. Sam Appleton, CEO, Ausdia Inc., will deliver the vision talk “The SDC ‘Root of Trust’ Problem, and How We Solve It,” addressing reliable timing closure throughout SoC design.
Dr. Ashish Darbari, CEO & CTO, Axiomise, will present the first keynote, “Power. Performance. Proofs: Scaling Formal for the AI‑Driven Compute Revolution,” focused on formal verification techniques for AI-focused custom silicon, including floating-point logic and PPA trade-offs.
A second keynote, “Re‑engineering Engineering for AI Chip Design, Verification, and Optimization,” presented bySridhar Seshadri, Senior Vice President, Engineering, Synopsys, highlighting AI-driven methods tailored to chip design and verification under power and performance constraints.

In addition to the invited talks, attendees can look forward to diverse technical tracks covering functional safety and security, static and formal verification, analog and mixed-signal verification, and more. The program will also feature contributions from Accellera’s Clock Domain Crossing and Portable Stimulus working groups, offering insights into the latest advancements in industry standards.

For program details and registration information, visit the DVCon India 2025 conference website.

To view the archives from past DVCon India conferences, visit here.

DVCon Europe

Join the design and verification community at DVCon Europe 2025, taking place October 14-15 at the Holiday Inn Munich City Center in Munich, Germany. This year’s conference will feature two keynote speakers, Amanda Brock, CEO of OpenUK presenting, “We Didn't Start the Fire…Open Source Software in 2025,” and Ralph Schleifer, head of Virtual ECUs and Simulation at CARIAD, highlighting “Driving Forward: The Evolution of Virtual Development in the Automotive Industry.”

There will be 10 company-sponsored tutorials and 10 industry tutorials, including “CDC-RDC Standardization: Concepts & Status,” presented by members of Accellera’s Clock Domain Crossing Working Group.

The two-day conference and exhibition will also highlight results from the SystemC Modeling Challenge. Sponsored by Huawei, participants will deliver short presentations showcasing their approaches to the question: “How well can you predict and analyze power consumption of a small application with a compact SystemC model?” Since March, participants have been developing their models and learning how to estimate power consumption at the system level. The challenge will culminate at the conference, where prizes will be awarded to the top performers.

In addition, DVCon Europe 2025 features a broad spectrum of technical paper presentations across system/IC design and verification, including engineering and research tracks covering topics such as AI/ML, functional safety, low-power and mixed-signal design, and IP reuse.

For program updates and registration details, visit the DVCon Europe website. Advance registration pricing is available through September 12.

To view the archives from past DVCon Europe conferences, visit here.

SystemC Evolution Day

Co-located with DVCon Europe, the 10th annual SystemC Evolution Day will take place on October 16 at the Holiday Inn Munich City Centre. This full-day, in-person workshop is dedicated to the ongoing advancement of the SystemC ecosystem through the evolution of its standards. The event features a series of focused sessions covering current challenges and forward-looking topics in SystemC standardization and development.

The program is in development. For the latest updates, visit the SystemC Events page.

To explore past workshops and access a wide range of SystemC resources, visit the SystemC.org community portal.

Accellera Draws a Crowd at DAC with Panel Highlighting Practical AI Gains

At the 62nd Design Automation Conference held in June in San Francisco, Accellera hosted a luncheon panel on the realities of AI in EDA, moderated by Dan Nenni of SemiWiki. Panelists from AMD, Cadence, Microsoft, Nvidia, Siemens, and Synopsys shared grounded perspectives on what’s working today and what lies ahead. Real applications already in production include PPA optimization, regression suite management, testbench generation, and even automated naming compliance fixes.

Looking forward, panelists highlighted agentic AI and multi-agent systems as the next frontier, with potential to deliver 30-50% productivity gains in verification flows. They also emphasized the importance of better data practices, trust, and interoperability standards to support adoption. The discussion underscored a key message: while full AI autonomy in EDA may be years away, AI is already providing real, measurable value, and momentum is building fast.

For more detailed coverage on the luncheon, check out Bernard Murphy’s article in SemiWiki.com “Insider Opinions on AI in EDA.”

More Resources

Missed DVCon U.S. 2025? Catch Up in the Archives!

Access the full library of papers, posters, presentations, and videos from DVCon U.S. 2025 in the DVCon U.S. gallery. You can also explore archives from past DVCon conferences around the globe, all in one place in the DVCon archive site.

Explore Hundreds of Accellera Videos On-Demand

Find the latest videos from our working groups, industry events and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

IEEE GET Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in over 220,000 downloads. The IEEE Get Program provides engineers and chip designers worldwide with no cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.