Join Us for Accellera Day at DVCon U.S. 2019

DVCon US 2017Monday, February 25
Design & Verification Conference and Exhibition
DoubleTree Hotel, San Jose, CA

Accellera invites you to join us as we open DVCon U.S. with a day focused on technologies that you can apply immediately and those that will help to define the future.

Agenda

9:00am-12:00pmTutorial: Gain Valuable Insight into the Changes and Features that are part of the new IEEE 1800.2 Standard for UVM and how to make the most of them

12:00pm-1:30pmAccellera Sponsored Luncheon

1:45pm-3:15pmWorkshop: SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC

5:00pm -7:00pmDVCon Expo and Reception


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Tutorial: Gain Valuable Insight into the Changes and Features that are part of the new IEEE 1800.2 Standard for UVM and how to make the most of them

We’ll dive into the changes and features that are part of the new IEEE 1800.2 standard for UVM. Attendees will benefit from Cliff’s favorite UVM tips and tricks, and he’ll offer clarification and guidelines for UVM messaging and verbosities. Cummings will also explain the origins of the two different techniques to define UVM transactions and execute sequences, including the advantages and disadvantages of each. With this knowledge, attendees will have a greater understanding of all publicly available UVM examples.

Speaker:
Cliff Cummings - Sunburst Design, Inc.

Organizer:
Barbara Benjamin - Accellera Systems Initiative


Accellera Luncheon

We hope you’ll join us for our annual Accellera Day luncheon where our Chair, Lu Dai, will provide an update on Accellera activities followed by the presentation of the 2019 Technical Excellence Award. We will then have a SystemC-focused panel that will explore what’s next for the standard where you will have an opportunity to ask questions and get answers to your most pressing questions.

All of Monday's attendees are invited to this Accellera-sponsored luncheon.

Panelists:
Stuart Swan - Mentor, A Siemens Business
Filip Thoen - Synopsys, Inc.
Mike Meredith - Cadence Design Systems, Inc.
Mark Glasser - NVIDIA Corp.

Moderator:
Laurie Balch - Pedestal Research


Workshop: SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC

SystemCThis Short Workshop on SystemC will provide an overview on High Level Synthesis (HLS) with a discussion on data types and model structure as well as lessons learned.  The presentation on HLS will be followed by a 30 minute tutorial on Functional Coverage for SystemC.  We’ll close the workshop with an update on the Accellera SystemC Working Group, with an opportunity for attendees to ask questions from the presenters.

Organizers:
Dragos Dospinescu - AMIQ
Mark Glasser - NVIDIA

High-Level Synthesis with SystemC: An Introduction

Writing a hardware design in SystemC model and using High-level Synthesis (HLS) to synthesize it to a register transfer level (RTL) model can yield many significant productivity benefits when compared to traditional RTL design flows. In this talk, we describe the fundamental structures of a SystemC design model, and what is abstracted in a SystemC model that is explicit in an RTL model. We then show how HLS tools are be used to concretize the abstraction into the desired structures in the RTL model, the productivity benefits and the remaining challenges in typical HLS flows.

Speaker: Frederic Doucet - Facebook

High Level Synthesis: Model Structure and Data Types

SystemC models used as input for synthesis must be properly structured. They differ in important ways from models used for virtual platform development and other purposes. Differences include restrictions in the C++ and SystemC constructs that can be used and a much greater use of SystemC bit-accurate datatypes and fixed-point datatypes.  The issues surrounding model structure and data types for synthesis will be discussed in this session.

Speaker: Mike Meredith - Cadence

High Level Synthesis: Lessons Learned

SystemC HLS usage has matured and product teams have used it for multiple generations of designs.   We present some lessons learned in wide-scale deployment.   We will cover some techniques for triaging HLS errors, how HLS fits in power flows, and techniques repurposed from the software engineering world to make code easier to maintain over multiple generations.

Speaker: Bob Condon - Intel

Functional Coverage for SystemC (FC4SC)

Functional coverage lies at the core of functional verification as the primary metric that assesses the quality of the entire verification process. This notion of functional coverage can be extended from the scope of RTL verification to the verification of any type of application.

The Functional Coverage for SystemC (FC4SC) is a header-only library that provides mechanisms for functional coverage definition, collection and reporting that can be used in any application which is compliant with the C++ standard, starting with C++11.

In this presentation, we will give you an introduction into FC4SC's capabilities, accompanied by examples of how to use the library for constructing and managing your coverage model. FC4SC use cases primarily involve (but are not limited to) measuring the level of exercise of SystemC models in order to track the features that are tested. This includes anything ranging from block level functional coverage, up to system level scenarios.  Reference: https://github.com/amiq-consulting/fc4sc

Speaker: Dragos Dospinescu - AMIQ

Accellera SystemC Working Group Update

A number of activities are currently underway within the Accellera Technical Working Groups that are of interest to the SystemC community.  Working groups involved in SystemC standardization cover the SystemC Language, SystemC Synthesis, SystemC Verification, SystemC Analog/Mixed Signal and SystemC Configuration, Control and Inspection.  A brief update on the activities of these working groups will be given.

Speaker: Mike Meredith - Cadence


DVCon Expo & Reception

A DVCon reception is a chance for conference attendees to network at the end of the each day. Come and enjoy cocktails and conversations in a casual environment with the DVCon Exhibitors. Mingle from booth to booth while enjoying food and drinks.

Thank You to Our Reception Sponsor:

Cadence

 


Thank you to our 2019 Global Sponsors

CadenceMentor GraphicsSynopsys