Community Newsletter: June 2023
IN THIS ISSUE:
- Message from the Chair
- New standards efforts, membership growth, conference expansion and more!
- Working Group Updates
- PSS video from DVCon U.S. 2023 available on-demand
- UVM 2020-2.0 Reference Implementation update available
- Interested in Federated Simulation?
- We are seeking input for a proposed working group to explore a new standard
- Accellera at the 60th Design Automation Conference
- Join us for a lunch panel focused on the SOC ecosystem
- Events Around the Globe
- DVCon Japan - June 22
- DVCon Taiwan - September 7
- DVCon India - September 13-14
- DVCon China - September 20
- DVCon Europe - November 14-15
- Call for Contributions for SystemC Events!
- Submit your ideas for our next Fika in September
- Session topics fill quickly! Submit proposals for SystemC Evolution Day
- DVCon U.S. 2023 Proceedings and More Available On-demand
- Recent Press Coverage
- SemiWiki covers standards, membership and our new scholarship
- SEMI newsletter Q&A with Bob Smith and Lu Dai
- IEEE Get Program Update
- Close to 165,000 downloads!
As we celebrate the beginning of summer, our work at Accellera continues. Our newest Clock Domain Crossing (CDC) Working Group has been moving as fast as wildflowers are blooming in California. Multiple subgroups within the working group are developing a Design Objective Document, with some already working on implementation.
Other working groups continue to meet actively and make significant progress. Our Functional Safety Working Group is days away from completing an updated whitepaper, and any day now the IP-XACT Working Group will be releasing supplemental material that aligns with IEEE 1685-2022. The Portable Simulus Working Group is focused on the 2.1 update to the standard.
Accellera continues to look at ways to help improve productivity, and for the past several years a group of enthusiasts has been pondering the challenge of cross-platform/cross-industry simulation, known as federated simulation. The discussion has gained traction with the exponential growth in electric vehicles and autonomous driving. Is your company delivering chips into a new industry and being asked to provide integrated simulation results? If so, how are you doing it? Would you like to see a standard in this area? We’re considering a Proposed Working Group to focus on federated simulation, so please contact us if you are interested.
As our work continues to grow and expand into new areas, so does our membership. I’d like to take this opportunity to welcome our newest Associate Members Apple, Blue Pearl, Microsoft, and Western Digital and our newest start-up members MachineWare and UniVista. I’m looking forward to the contributions of these new members to our design and verification standards efforts.
Our DVCon conferences continue to expand around the globe. Our newest addition is in Taiwan in September. It is very exciting to bring DVCon to another important region in the world. I am looking forward to attending and delivering the conference’s first keynote.
Our first in-person DVCon Japan is next week. The first conference was virtual last year, and everyone is looking forward to a full day gathering of the best design and verification minds in Japan.
For those of us in the U.S., we hope to see you at the Design Automation Conference in San Francisco in July where the conference is celebrating its 60th anniversary. Accellera will be hosting a luncheon on SoC design and verification challenges with a focus on the efforts of our CDC Working Group. It will be a great opportunity to hear from industry veterans, both users and vendors, discussing what we can do with open standards and methodologies.
I hope to see you in San Francisco or one of our other events this year.
Accellera Systems Initiative Chair
DVCon U.S. 2023 Portable Stimulus Video Now Available
The Portable Stimulus Working Group presented “User Experiences with the Portable Stimulus Standard” at DVCon U.S. 2023 in March. Presenters Prabhat Gupta from AMD and Mike Chin from Intel discussed their experiences with PSS 2.0. Tom Fitzpatrick, Vice Chair of the working group, gave an overview of new features included in the upcoming update to the standard. He also discussed the removal of C++ to the standard and the introduction of Behavioral Coverage. Following the technical presentation, members of the working group held a panel discussion that is also part of the recording. View this informative presentation, including audio, here.
For more information on the Portable Stimulus Working Group, including a list of resources, visit the working group page.
To provide comments or ask questions regarding the standard, visit the community forum.
The UVM Working Group has updated the UVM 2020-2.0 Reference Implementation (RI) to reflect the 2020 update to IEEE 1800.2. Updates include substantial performance improvements as well as enhanced backward-compatibility with code written for UVM1.1d and UVM1.2. Download the latest updates to the UVM standard here.
For more information on the UVM Working Group, including links to additional resources, visit the working group page.
Accellera Seeks Input for Proposed Working Group to Explore Federated Simulation Standard Development
Accellera is initiating a Proposed Working Group (PWG) to identify industry interest in developing a standardized communication interface to enable interoperability of virtual modeling, simulation, and integration throughout the product lifecycle. The intent of this communication standard is to facilitate the creation of a distributed and orchestrated (“federated”) multi-domain simulation framework, compatible with and complementary to existing approaches used in different industries and sectors.
Accellera will host a teleconference on Tuesday, July 18 from 8am-9am PT to introduce the PWG, its charter, motivation, objectives, and initial plans. If you would like to participate in the conference call, register here. The official start of the PWG is planned for September 2023, and will be a full day face-to-face event for those interested in meeting to discuss the proposed standard. If you have questions or would like to know more about this PWG to develop a Federated Simulation Standard, please get in touch.
Topic: Tackling SoC Integration Challenges
As System-on-Chip (SoC) design becomes more widespread, the challenge of integration of design IP created and verified by tools from different suppliers becomes much more of an issue. To tackle these challenges, Accellera working groups have introduced new standardization initiatives such as the Security Annotation for Electronic Design Integration (SA-EDI) 1.0 Standard, which is focused on helping IP providers identify security concerns, and the new Clock Domain Crossing (CDC) Working Group, which is focused on creating a standard for CDC abstraction models to facilitate faster design IP integration.
The Accellera luncheon will begin with an update from Chair Lu Dai, followed by a panel focused on the efforts of the CDC Working Group to define a standard CDC collateral specification. The standard is aimed at easing SoC integration, enabling teams to integrate IPs verified using various CDC tools without sacrificing quality and design time. The 85 current members of the working group represent 20 companies, including a variety of users and tool vendors. Panel members from the working group will share the key work in progress as well as discuss deliverables for the coming year. There will be an opportunity for questions from attendees.
Organizer: Dammy Olopade, Intel and CDC Working Group Chair
Moderator: Paul McLellan, Editor of Breakfast Bytes
The Accellera-sponsored luncheon is free to DAC attendees, but registration is required.
The first in-person DVCon Japan will be held June 22 at Kawasaki Industrial Promotion Hall. Held virtually last year, the Steering Committee is eager to meet face-to-face with attendees this year. The keynote, “Principles and Prospects of Language Generative AI” will be presented by Professor Yoshimasa Tsuruoka of Tokyo University. There will be eight tutorials and 12 papers presented during the full day technical conference. Topics include RISC-V, IP-XACT, Portable Stimulus, UVM, RTL Verification, and much more.
Read the Welcome Message from DVCon Japan 2023 Executive Committee Chairman Genichi Tanaka here.
DVCon expands in Asia! To meet the growing interest in design and verification solutions, standards, and methodologies, the first DVCon Taiwan will be held September 7th. Registration is now open and the advance program is available. Lu Dai, Accellera Chair, will give the opening Keynote Address for the first edition of the new conference.
Welcome Message from DVCon Taiwan 2023 General Chair Penny Yang:
The COVID-19 pandemic has forced everyone to engage in the ubiquitous use of IC technology. To be able to handle all kinds of new and hard problems for IC design and verification, we cannot just be an independent player anymore. A conference allows engineers to stand on experts’ shoulders and brainstorm with a team to develop creative solutions effectively. It will be of benefit to both juniors and seniors.
However, few Taiwanese companies allow engineers travel to other regions for conferences. And the pandemic just made the need more acute. It is always better to have a face-to-face event so that more engineers can network in person. Therefore, even though there are DVCons in U.S., Europe, India, China, and Japan, we still want to propose a DVCon in Taiwan.
As you may know, there are hundreds of engineers in the IC design industry in Taiwan. However, currently, there is no cross-company/cross-vendor conference in Taiwan to gather all of the design and verification engineers, professors, and students in this field. For the conferences held by EDA vendors in Taiwan, DV is just a small part and may be more on tool introduction. We expect DVCon Taiwan to be more neutral and technical so that more talents can easily join from every institute.
Besides, there is almost no involvement of Taiwanese engineers/companies in Accellera standards currently. Most Taiwanese engineers are users, but do not participate in Accellera working groups. We can encourage more involvement/usage by DVCon Taiwan.
From the experience of 2013 Accellera User Forum in Taiwan, the attendees could be up to 200. Currently, we have created a group in LinkedIn, DVCon Taiwan 2023, with 233 members from 60 companies/institutes, and it will be increased.
Finally, we have planned the 1st DVCon Taiwan in-person conference on September 7, 2023 in Hsinchu NYCU. On behalf of the whole steering committee, we welcome all friends to join us. We will invite experts from the industry to share the hottest trends. We also encourage you to step on the stage and share your intelligence with us.
Looking forward to meeting you in DVCon Taiwan.
DVCon Taiwan 2023 General Chair
For more information, including the latest updates to the program, visit the conference website.
Showcase your company expertise and engage with the community by sponsoring a workshop or tutorial. The submission site for proposals is open through June 30. The workshops are 45 minutes in length and the tutorials are 90 minutes.
Welcome Message from Pradeep Salla, DVCon India 2023 General Chair:
On behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13-14th September 2023 as an In-Person conference. We want to carry forward the momentum, excitement, and enthusiasm witnessed during last year’s edition of DVCon India 2023. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey.
This year’s edition will have a good blend of Vision and Keynote talks, lively panel discussions, tutorials, and technical sessions spread across both days. We are looking at some of the feedback to see how to set an agenda that provides key takeaways to everyone at the conference.
This conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation, Methodology & Automation, Functional Safety & Security, Low Power and Mixed Signal Design, Static and Formal methods and Digital Twins and SystemC Modeling and New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation, Big Data analysis and new algorithms in HW/SW co-design and co-verification. We want to remind you that this isn’t just a Verification conference, but a Design AND Verification conference, and we want to ensure that the Design community has greater participation.
This year, we will be expanding our Technical Program Committee, and we want to make it even stronger than what it is now. The entire team is planning and putting in the extra hours to ensure we deliver a world class technical conference, and am sure you will participate to elevate the conference experience.
We invite the entire technical fraternity from the ecosystem to actively participate, engage, share learnings with the rest of the community and take an enthusiastic part in DVCon India 2023 and make it a grand success!
For more information and the latest updates on DVCon India, visit the conference website.
The Call for Sponsored Workshops and Tutorials is open through June 28. For more information on suggested topics and submission requirements, visit here and click on the “conference” tab.
Registration for DVCon China is now open, with advance rates available through August 14. For more information on the conference, visit the conference website. You can also follow DVCon China on WeChat.
Welcome Message from PeiYu Liu, DVCon China 2023 General Chair
I am honored to be the chair of DVCon China again. On behalf of the whole steering committee, we welcome all old and new friends to join us. As a platform focused on technology, we’d like to bring you latest update from the industry, new ideas, and new practices from engineers all over the country.
In 2021, DVCon China got another record of participants. People were shocked by how hot the industry was. Most of my friends were busy on their chip tapeouts or publishing their new EDA tools. Unfortunately, we see some ebb and flow of industry these days. But why not take it as an opportunity to review our work—are you really doing something cool or just homogeneous work?
I think people won’t be that surprised if some papers this year are with the help of ChatGPT. These days AI really gives us a heads up, and we need to rescue our engineers from chores and focus on key technology. There is no doubt that AI will generate most of the code instead of us one day. Hopefully he still needs to follow our instructions until he can create something new like UVM/PSS/formal by himself. So, what is our competence compared to machines? I think creativity is on top of the list. We keep finding smart ways to improve our efficiency and quality, based on current tools and methodologies, or our customized solutions. Keep thinking, and each of your interesting ideas may become a standard or direction followed by everyone. Then let ChatGPT write the code.
We’re going to have many topics in DVCon China. We will invite experts from the industry to share the hottest trends. We also encourage you to step on the stage and share your intelligence with us. Looking forward to meeting you in Shanghai!
The proceedings from the 2021 conference are available. The 2022 conference was postponed due to the pandemic.
New to the program this year is a highly anticipated research track. The program committee is seeking high quality research papers to be included in the new track. The deadline to submit a research paper for consideration is July 17. Those that are accepted will be published as scientific papers in the IEEE Digital Library. For more information and submission guidelines, view the Call for Research Papers.
For the latest updates on DVCon Europe, including advance program availability and registration information, visit the conference website.
To view the videos from DVCon Europe 2022, visit here.
In addition to our SystemC Evolution Day events, Accellera’s SystemC community has been holding smaller, online workshops called SystemC Evolution Fikas. The workshops are referred to as Fikas to honor the Fika tradition of sharing a coffee, slowing down a bit, and sharing topics of interest.
The next Fika will be held in early September. The organizing committee would like your input on the topics you’d like to see covered or that you might like to present. The single-day online workshops are free to attend, and each session is about 45 minutes. If you have topics that you’d like to see included in an upcoming Fika, please email firstname.lastname@example.org. If you’d like to present a topic, please include a brief abstract in your email.
To view past presentations from Fikas or SystemC Evolution Day, visit the SystemC Evolution event page.
SystemC Evolution Day
Co-located with DVCon Europe, the 8th annual SystemC Evolution Day will be held November 16 at the Holiday Inn, Munich, City Centre. The workshop is a full-day in-person event focused on the evolution of SystemC standards to advance the SystemC ecosystem. It is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards.
The day is divided into several in-depth technical sessions. The organizing committee is seeking input on topics that attendees would like to see covered as well as abstracts for proposed presentations. To provide input or proposals, email email@example.com.
If you missed a session during DVCon U.S. 2023 or want to learn more about a particular topic, the material is available on-demand. Browse the public DVCon archive site for papers, presentations, posters, and videos from past conferences. You can search by year, region, type, or topic for the conferences China, Europe, Japan, and the U.S.
Interested in Brushing Up on Standards this Summer?
Visit the Accellera’s Vimeo site for access to hundreds more videos available on-demand.
SemiWiki: SemiWiki’s Bernard Murphy sat down with Accellera Chair Lu Dai during DVCon U.S. for an update on Accellera working groups, membership, and the new Stanley J. Krolikoski scholarship. Read the article here.
SEMI Newsletter: Bob Smith, Executive Director of ESD Alliance, a SEMI Technology Community, and Lu Dai discussed the importance of semiconductor standards in a recent Q&A for the SEMI newsletter. The full Q&A discussion is available here.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in close to 165,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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