Community Newsletter: August 2015
IN THIS ISSUE:
- Message from the Chair
UVM 1.2 joins growing list of standards contributed to IEEE-SA
- DVCon Global Focus
The latest updates on DVCon India, Europe, and U.S
- SystemC Japan
Engineers in Japan enjoy a full day of SystemC education
- Accellera in the News
UVM 1.2 delivered to IEEE-SA and SCE-MI 2.3 updates
- Scheduled Working Group Meeting
Portable Stimulus Working Group to meet October 13th
- Featured Video Tutorial
"Next Generation Design and Verification Today" now available
We are very proud to have contributed our latest standard, UVM 1.2, to the IEEE Standards Association for further standardization and ongoing maintenance. As a standards organization, our members are dedicated to the development of standards that will help to advance design and verification productivity for electronic products worldwide. As a result of our ongoing collaboration with the IEEE-SA, we have reached another significant milestone with the delivery of UVM 1.2. It joins Accellera standards IP-XACT, SystemC, SystemVerilog, Verilog, VHDL and UPF that are now being advanced and maintained by the IEEE.
Our joint efforts with the IEEE-SA will continue to make more standards available for use by design teams around the globe. We look to our members to help initiate the next standards development efforts to ensure that we are providing what electronic design teams need most as they are tackling their most difficult issues during the design and verification process. We are in the midst of the early development stages of the Portable Stimulus Working Group, launched with its first meeting in February at DVCon U.S., and we look forward to working with our members and our community for the development of the next generation of standards.
Shishpal Rawat, Accellera Systems Initiative Chair
DVCon currently has three conferences around the globe: DVCon U.S., DVCon India and DVCon Europe. All DVCon conferences are designed to provide information to attendees that is highly technical and directly applicable to their daily work.
DVCon, an Accellera Systems Initiative sponsored event, has been the most important conference for working professionals, industry leaders and EDA vendors in the field of electronics design and verification. While the U.S. edition of DVCon has been around for more than 25 years, in 2014, Accellera decided to expand its reach to other continents as well. In August of last year the first ever DVCon India was organized with strenuous efforts from the local organizing committee members. With a good share of the world’s design and verification being done in India it came as no surprise to all that the local ecosystem welcomed this flagship event with open arms. The local talent was more than eager to present their innovations and challenges in the design and verification space. DVCon India has become a name that many in India want to be associated with quickly. Fast forward to 2015; Accellera continued its efforts to organize DVCon India 2015 with much of the local support being intact. This year DVCon India attracted more proposals, tutorials, panels and exhibits as the industry expects high quality content to be delivered by Accellera.
The program is spread over two days; Day1 is packed with several keynotes, invited talks and panels with several industry experts as panelists. Day2 brings to the attendees papers covering a wide range of topics on both DV and ESL tracks. The complete agenda for this year’s DVCon India is available at dvcon-india.org/conf/program-at-a-glance/.
Online registration is now open at dvcon-india.org/registration/.
As a value-add to the participants and the event sponsors, DVCon India has an elaborate exhibit space with regular booths and special booths for start-ups with tight budgets. If you are looking to showcase your products and offerings, contact the DVCon India team right away to book your space. There are also several sponsorship packages available for interested parties, please visit: dvcon-india.org/exhibition/exhibitor-opportunities/ for more details.
On behalf of DVCon India team we invite you to be there at the event and have fun!
Registration will open on September 1st for DVCon Europe, to be held on November 11th and 12th 2015 in Munich, Germany. Preparations for the show are well underway, building upon the tremendous success of last year’s show.
The program committee has accepted approximately 26 papers and 16 posters covering varied design and verification topics with a practical engineering angle. Included are papers on advanced verification, intricate design issues, methodologies revolving around Accellera standards such as UVM and SystemC, as well as emerging proposals. Tackling high-end design issues such as functional safety solutions, mixed signal architectures and low power methodologies will be at the forefront of the show.
A full complement of eight tutorials on topical subjects and two panels on the constraints of automotive design and future verification trends complete a fascinating ensemble of useful, practical engineering information. The program overview will be announced on September 1st. #DVConEurope
This year 22 exhibitors have already signed up with more to follow, and 350 or more attendees are expected. This makes it an unparalleled networking event for European System, ASIC and FPGA engineers, and various events are planned to bring everyone together. Don't wait — we’re expecting another sold out show.
Please note that DVCon Europe 2015 coincides with two very large trade fairs in Munich, so you are advised to book your travel and accommodation early.
DVCon U.S. will be held February 29th – March 3rd, 2016 at the DoubleTree hotel in San Jose, CA. The premier conference focused on the practical use of specialized design and verification languages, DVCon U.S. has issued its Call for Extended Abstracts (deadline September 10), Call for Tutorials (deadline October 2) and Call for Panels (deadline October 2).
Approximately 300 engineers filled a ballroom during SystemC Japan in June for a full, intense day of technical talks. Held annually, the conference draws engineers from around the region with a thirst for continuing education on SystemC. Kicking the day off was a talk given by Dr. Stan Krolikoski, Accellera board member, followed by twelve in-depth technical presentations. An evening reception rounded out the conference, with vendors available to provide information on their products.
- In July we announced that UVM 1.2 has been transferred to the IEEE for further standardization and maintenance. Designated IEEE P1800.2 within the IEEE Standards Association, a working group has been formed and held its initial meeting on August 6. View Call for Participation to get involved.
- Last week Accellera announced updates to the Standard Co-Emulation Modeling Interface (SCE-MI). SCE-MI 2.3 gives engineers more flexibility in their verification flows. A free download is available.
"Next Generation Design and Verification Today" video tutorial now available
Accellera working groups are focused on solving specific problems key to raising the efficiency of our industry and forming a design and verification foundation for all to use. However, when problems that need to be solved need more than one technology, the community can apply existing standards in novel ways by connecting them together to solve next-generation problems today. Delivered at DVCon U.S. 2015, this tutorial explores how the SystemVerilog, UCIS, UPF, and other standards are applied in interesting ways to push the electronics industry. View tutorial.
Watch more tutorials at videos.accellera.org.
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Copyright 2015 Accellera Systems Initiative