Community Newsletter: February 2022
IN THIS ISSUE:
- Message from the Chair
- Much to look forward to in 2022, from our online resources to news from our working groups
- EDACafé interviews Lu Dai
- Accellera Standards Focus at DVCon U.S. 2022
- Sessions from our Portable Stimulus, UVM-AMS, IP Security, Functional Safety, & UVM working groups
- Upcoming Events
- DVCon U.S. 2022 – Program and Expo on exciting interactive platform
- DVCon China 2022 – April 27 in person in Shanghai
- SystemC Evolution Fikas
- DVCon India 2022 – Save the date!
- Post-Event Summary – DAC 2021
- SystemC Evolution Day Videos Now Available!
- IEEE Get Program Update
We hope 2022 is off to a good start for you. While we are all hoping the pandemic will soon be ending, the recent surge in the Omicron variant is a sober reminder to stay vigilant as we are not out of the woods yet. Fortunately, we are better prepared now than when the pandemic arrived in early 2020.
With the world more engaged online versus in-person these past couple of years, Accellera has significantly expanded its online presence. We have a wealth of information available including Language Reference Manuals, Proof of Concept software, ongoing discussions in our forums, and many videos, including tutorials and workshops from working group participation in various conferences. We also continue to expand the content in our systemc.org community portal. It is a terrific entry point for those looking for a valuable resource for information related to SystemC.
Accellera places the safety and wellbeing of our community first, and as a result the upcoming DVCon U.S. will again be virtual. We have a full agenda with exciting topics and fresh content for all attendees. With our virtual conferences available on-demand, attendees are no longer constrained by travel or time zones, so please take the opportunity to join us online. We hope to return to in-person conferences for the second half of the year - stay tuned!
Although we are barely into 2022, our working groups are already making huge strides. The Functional Safety Working Group is moving full-steam ahead developing their 1.0 draft standard and the UVM-AMS Working Group is putting the finishing touches on their whitepaper. IP-XACT will have an official update to its IEEE 1685-2014 standard in the coming months, along with a reference implementation shortly thereafter. Other working groups are also quite busy incorporating user feedback gathered through our online forums to their standards efforts. If you would like your feedback and comments incorporated into the standards that are important to you, whether they are being developed or updated, we encourage you to visit our forums and voice your opinion.
From all of us at Accellera, we wish you a happy, safe, and productive 2022.
Lu Dai, Accellera Systems Initiative Chair
For some insight into the latest Accellera working group activities, view the interview with our Chair, Lu Dai and Sanjay Gangal, EDACafé. Lu also discusses what you can look forward to from Accellera in the coming year and beyond, as well as the benefits of membership.
Monday, February 28
The tutorial will highlight the power and flexibility of Accellera’s Portable Stimulus Standard by walking through several real-world examples. Beginning with a brief overview of the standard, presenters will show how to use PSS to model stimulus for a variety of applications, from which multiple target-specific test implementations may be generated.
UVM-AMS Working Group Workshop
Monday, February 28
The UVM-AMS Working Group was formed with a charter to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM, with major focus on transient analysis. The UVM-AMS standard will provide a comprehensive and unified analog/mixed-signal verification methodology based on UVM to improve analog/mixed-signal (AMS) and digital/mixed-signal (DMS) verification of integrated circuits and systems. This will encourage support by tool and IP providers, offering ready-to-use analog/mixed-signal verification IP that can be integrated easily into a UVM-AMS testbench. It will raise the productivity and quality of analog/mixed-signal verification across projects and applications, thanks to the reuse of proven verification components and stimuli. In this workshop, the working group will share the findings, requirements, and ideas collected so far and the next step plan for developing the proposed standard. Aspects under consideration for the UVM-AMS standard will be discussed at high level in this workshop.
In addition, an example will be provided to illustrate how UVM-AMS may be deployed to easily augment an existing UVM environment to verify an analog/mixed-signal device under test.
Presenters will conclude with an opportunity for attendees to ask questions and comment on the proposed standard.
IP Security Assurance Working Group Workshop
Monday, February 28
The importance of security in the electronic systems on which many of us rely has become obvious to semiconductor design and manufacturing companies, but most hardware security assurance practices in the industry are still performed manually using proprietary methods. This approach is very expensive, time consuming, and error prone due to the ever-increasing complexity of systems. To address the issue, the Accellera IP Security Assurance (IPSA) Working Group was formed in 2018 by a team of security and EDA experts to work on developing a general and portable IP security specification standard to describe the IP security concerns (threat model) and to guide EDA vendors on how to produce security assurance collateral and use it for the automation of security verification. The specification was approved as an Accellera standard for Security Annotation for Electronic Design Integration (SA-EDI) in 2021.
During this workshop we will give an overview of this standard by going over the related collateral, methodology, a case study of the application of the standard, and the roadmap of the standard.
Functional Safety Working Group Workshop
Monday, February 28
This workshop presents an update on the work performed by Accellera’s Functional Safety Working Group over the past year and gives a preview of the white paper the group is planning to publish in 2022. The presentation first introduces the formalization of the Failure modes, effects, and diagnostic analysis (FMEDA) process and how it has led to the initial high-level definition of the data model, which will be the basis for the emerging functional safety standard.
The workshop will then provide detail on the data model and describe the necessary attributes to perform an FMEDA, followed by a description of some of the methodology discussions that are captured or assumed in the data model.
The workshop will also explore some directions connected to the development of the Functional Safety data format standard that the working group has identified and that will form the basis for the next steps for the working group.
UVM Working Group Birds of a Feather
Wednesday, March 2
During the UVM Birds of a Feather meeting at DVCon U.S. 2021, the Accellera UVM Working Group heard from users how backward compatibility issues held back migration to the latest library. The working group is preparing to release a new library version (targeted for summer 2022) that reduces these issues greatly.
At the 2022 meeting, the working group will present the expectations for this library, including the few remaining situations that may require user code updates, to again get feedback from the user community. There should also be time remaining for an open Q&A. Attendance to the Birds of a Feather is free, but registration through DVCon is required to access the platform.
DVCon U.S. 2022
“We have an exciting technical program in store for attendees,” stated John Dickol, DVCon U.S. 2022 Program Chair. “This year we added another layer to our already rigorous paper review process, helping to ensure attendees receive the quality program they’ve come to expect from DVCon. Attendees can look forward to sessions covering low power, RISC-V, UVM, machine learning, portable stimulus, functional safety and much more. In addition to 42 paper presentations, we’ll have 15 poster presentations, two panels, four tutorials, and 11 workshops throughout the four-day program.”
The virtual program this year will be expanded to include an exciting new interactive platform, Gather.Town. It offers more opportunities for attendees and presenters to interact with each other in a more natural way, being able to “walk” in and out of conversations with ease. It is intended to enhance the exhibit hall and networking experience for all DVCon participants.
The keynote for the 2022 program, “Unleashing AI/ML for Faster Verification Closure,” will be presented by Manish Pandey, Vice President of Engineering, Synopsys on Tuesday, March 1 at 1:00pm. The keynote will explore how exploiting supervised, unsupervised, and reinforcement learning has enabled an order-of-magnitude gain in closure convergence and verification cycle reduction.
Two panels will be offered on Wednesday, March 2. The first panel, “The Meeting of the SoC Verification Hidden Dragons,” will discuss the gap formed in semiconductor verification between block functional verification and system SoC validation. Panelists will compare methods from different verification viewpoints, hashing out the pros and cons while taking input from the virtual audience. The second panel, “Going Faster - How to Cope with Shrinking Schedules and Increasing Complexity,” will focus on the factors that are putting pressure on design verification schedules, the problems with current approaches, and what comes next.
Registration is open. Registration for the keynote, panels, UVM Birds of a Feather, and exhibits is free.
For the latest updates regarding the conference and expo, please visit the website.
DVCon China 2022
Welcome Message from PeiYu Liu, DVCon China 2022 General Chair
“I am honored to be the chair of DVCon China again. On behalf of the whole steering committee, we welcome all the old and new friends to join us. As a platform to focus on technology, we’d like to bring you the latest updates from the industry, new ideas and new practices from engineers all over the country.”
Read the full welcome message here.
Visit the DVCon China 2022 website for the most up-to-date information.
SystemC Evolution Fikas
In addition to the SystemC Evolution Day annual event, SystemC fikas are offered as smaller online workshops. Referred to as Fikas to honor the Swedish tradition of sharing a coffee, slowing down a bit, and talking about things that the participants care about. These virtual fikas are free of charge.
If you have topics that you think should be included in an upcoming fika, please email firstname.lastname@example.org.
For more information and to view presentations from past fikas, visit the event page.
Save the date! DVCon India 2022 will be held September 6-7. It is currently planned for an in-person conference and exhibition. Please check the website for the most up-to-date information.
To view videos from DVCon India 2021, please visit here.
Accellera sponsored an informative in-person town hall discussion focused on Functional Safety at the 58th DAC in December. Approximately 70 attendees heard from Functional Safety Working Group Chair Alessandra Nardi and participants Alex Palus, AMD; Ghani Kanawati, Arm; Bharat Rajaram, Texas Instruments; and Serge Leef, DARPA on the challenges that lie ahead, as well as what to look forward to as the future of Functional Safety unfolds. Alessandra also provided insight into the timeline for Accellera’s emerging Functional Safety standard.
Media coverage from the event includes:
- Electronics Weekly: “Design Rules for Functional Safety are Explored at DAC”
- SemiWiki: “DAC 2021 - Accellera Panel all about Functional Safety Standards”
SystemC Evolution Day is a full-day interactive technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. New videos from the October 2021 event are available on a variety of SystemC topics, including SystemC in hybrid simulations, formal verification for SystemC/C++ designs, multi-core debugger integration, and a discussion focused on the SystemC community’s GitHub, forums and other resources. For more information on SystemC, visit the new SystemC.org community portal. The portal is intended as an online reference for everything related to SystemC, including standards and implementations, training, forums, videos, and many other resources.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 139,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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