Community Newsletter: May 2025


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative ChairAs we reach the mid-point of the year, I’m excited to share the strong momentum across our community.

DVCon China concluded last month with great success, matching its highest attendance to date. It has clearly established itself as a premier technical event in the region, one that engineers attend to learn, collaborate, and engage with colleagues on the latest in design and verification, acquiring knowledge that they can apply directly to their current projects.

Our working groups continue to make impressive progress. The Functional Safety Working Group has moved its data model into ballot, laying the foundation for its forthcoming Language Reference Manual (LRM). The Clock Domain Crossing Working Group released version 0.5 of its LRM to the public and is on track for a 1.0 release later this year. The Federated Simulation Standard Working Group continues to draw strong participation, and the Portable Stimulus Working Group shows no signs of slowing down, building on its recent 3.0 release and DVCon U.S. workshop, the group is already hard at work on version 3.1 of the standard.

SystemC activity remains vibrant, with the Analog/Mixed-Signal LRM in draft form and on schedule for a handover to the IEEE this summer. In addition, the SystemC Language, Control Configuration and Inspection, and Synthesis Working Groups are all actively advancing their respective efforts. The SystemC Verification Working Group has welcomed a new chair who will help drive continued alignment with UVM, and the SystemVerilog-MSI Working Group is reviewing additional contributions to its draft standard, causing a slight delay, but they remain on course for a release later this year.

I’d also like to extend a warm welcome to Cariad/Volkswagen, Altair Engineering, IBM, Samsung, and Google as the newest members of the Accellera community.

Lastly, as the 62nd Design Automation Conference approaches, I invite you to join us at our luncheon on Tuesday, June 24, where we’ll explore how we’re embracing the opportunities and unique challenges AI presents in the design and verification space. We look forward to seeing you there!

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

News from Accellera Working Groups

New SystemC Summer of Code Program

SystemC Summer of Code logoAccellera has launched the SystemC Summer of Code (SSoC) 2025 program, offering students an opportunity to contribute to the evolution of the SystemC ecosystem. This 12-week program, running from May through August, pairs selected students with experienced mentors to work on real-world projects that enhance the Accellera SystemC reference implementations. Participants will collaborate closely with Accellera's working groups.

The 2025 edition features several impactful project areas, including:

  • Advancing the SystemC Build and Test Flow Using Continuous Integration (CI): Improving automation and quality of Accellera’s SystemC reference implementations.
  • SystemC Control Interface: Developing an API to introduce a control interface for system-level models.

Each project is designed to provide students with valuable experience in areas such as C++, SystemC, CMake, and Git. The program will conclude with a wrap-up phase in September and October, where students will present their work to the respective Accellera working groups.

For more information about the SystemC Summer of Code 2025 program, including project descriptions, please visit the SystemC Community Portal.

Clock Domain Crossing Working Group Draft Standard 0.5 Public Review Update

The public review of Accellera’s Clock Domain Crossing (CDC) Draft Standard 0.5 was open April 15-May 15, 2025. The review period generated valuable feedback from both EDA tool vendors and product companies. The comments focused on the newly introduced content in the Language Reference Manual (LRM), including topics related to format, assertions, testing, and output collateral attributes.

Working group members are actively addressing the feedback, with additional working sessions initiated to support the update process. The working group will incorporate feedback into its upcoming 1.0 standard.

For more information on the CDC standardization effort, visit the Accellera CDC Working Group page.

Download the New Federated Simulation Standard Whitepaper!

Today’s industries often address modeling and simulation challenges in isolation, resulting in a patchwork of incompatible standards and tools. The new Federated Simulation Standard (FSS) aims to change that by introducing a unified, cross-industry framework designed to enable interoperability, seamless integration, and greater reuse of simulation technologies. Learn more in the new Federated Simulation Standard Whitepaper.

 

Accellera at the 62nd Design Automation Conference (DAC)

Join Accellera for a Luncheon Panel at DAC

DAC 2025 logo“Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?”

Tuesday, June 24
12:00-1:30 pm
Room 2006, Moscone West

Register Now button

Join us at DAC for an insightful luncheon panel sponsored by Accellera, where industry leaders will discuss the transformative role of AI in semiconductor design and verification. As AI rapidly evolves, its potential to reduce costs, shorten time-to-market and address impending talent shortages is becoming increasingly evident—but what are the real-world opportunities and challenges?

Our panel brings together industry experts to share their vision and experiences, examining:

  • The impact of AI on design and verification flows
  • Envisioned benefits of applying AI, including cost reduction
  • Challenges in training and deploying Large Language Models (LLMs), including IP ownership, ethics, and security
  • The role of industry standards to shape AI-driven methodologies

Moderator: Daniel Nenni, Founder, SemiWiki.com

Panelists:

  • Chuck Alpert, Cadence Fellow
  • Erik Berg, PhD, Microsoft Sr. Principal Engineer, Verification
  • Monica Farkash, PhD, AMD Fellow, Verification
  • Harry Foster, Siemens Chief Scientist Verification
  • Badri Gopalan, Synopsys Scientist, AI/ML
  • Syed Suhaib, Nvidia Director of Engineering, Verification

The Accellera-sponsored luncheon is free to DAC attendees, but registration with Accellera is required.

Engineering Special Session: CDC-RDC Interoperable Collateral Standardization

Join Members of the Clock Domain Crossing Working Group at DAC

Monday, June 23
10:30-12:00 pm
Room 2008, Moscone West

This special engineering session will revisit the fundamental concepts and constraints of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC). It will also present an overview of the recommended reference verification flow. In addition, the session will outline the goals, scope, structure, and deliverables of the Accellera CDC Working Group, with a focus on developing a specification of the abstract model.

Engineering sessions are open to registered DAC attendees.

 

IEEE Standard 1801™-2024 (UPF 4.0) Now Available for Download Through the IEEE GET Program

UPF logo

The recently published IEEE Std. 1801™-2024 Unified Power Format (UPF) 4.0 Standard, which specifies and verifies low-power intent, is now available for download fee-free, courtesy of Accellera as part of the IEEE GET Program.

“Our collaboration with the IEEE Standards Association empowers design and verification engineers worldwide with fee-free access to leading-edge standards,” stated Lu Dai, Accellera Chair. “By providing IEEE Standard 1801™ through the GET Program, we offer designers a valuable resource to explore, craft, verify, and apply power-aware concepts to electronic systems and deliver power-aware silicon IP. This accelerates learning and adoption, fostering a global community with a shared foundation of knowledge and best practices.”

IEEE Standard 1801, also known as UPF, is a standardized specification language designed to define the low-power architecture of an ASIC. It streamlines integration throughout the entire verification and implementation process. Built on Tool Command Language (TCL), UPF complements existing hardware description languages such as SystemVerilog and VHDL. It allows designers to specify essential power management elements such as power domains, supply networks, power shutoff, and multi-voltage designs.

Read the full press release >

Video of the IEEE 1801™-2024 Workshop at DVCon U.S. 2025 Available for Download

UPF logo

The IEEE 1801-2024 UPF 4.0 workshop at DVCon U.S. 2025 provided an overview of key enhancements to the Unified Power Format standard, addressing the growing complexity of low-power designs and the need for improved IP reuse, analog/digital co-verification, and state retention modeling. Attendees were introduced to important new concepts such as virtual supply nets, refinable macros, UPF libraries, and Value Conversion Methods (VCM), as well as features that better define interfaces between analog and digital components.

The workshop focused on the most impactful updates that support real-world design needs, offering insight to help engineers transition to the new standard and improve the reliability and flexibility of their low-power design methodologies.

View the IEEE-2024 UPF 4.0 video >

 

Karsten Einwich Receives the 2025 Technical Excellence Award

Karsten Einwich

Karsten Einwich, a member of the SystemC AMS Working Group, was presented with Accellera’s Technical Excellence Award during the Accellera-sponsored luncheon at DVCon U.S. 2025.

“Karsten’s contributions to the advancement of the SystemC AMS standard have been instrumental in enriching the SystemC ecosystem,” stated Martin Barnasconi, Accellera Technical Committee Chair. “His deep expertise in mixed-signal system modeling and SystemC brings tremendous value to the community. Moreover, his unwavering dedication to developing the SystemC AMS proof-of-concept implementation exemplifies the successful coexistence of open-source contributions and commercial EDA offerings. It is my distinct honor to have presented Karsten with the 2025 Technical Excellence Award.”

Einwich has played a pivotal role in advancing the SystemC AMS standard. More than two decades ago, recognizing the importance of industry alignment and the standardization of the SystemC AMS language extension, he joined a study group to initiate these efforts. His work began within the Open SystemC Initiative (OSCI), which later became part of Accellera. Through his contributions, Einwich contributed to the definition of the SystemC AMS standard, IEEE Std. 1666.1, and he delivered a standard-compatible reference implementation to support the deployment and adoption of SystemC AMS as the first standardized and open system-level modeling language for mixed-signal applications.

Read the full press release >

 

Upcoming Events

DVCon Japan 2025 Set to Bring the Design and Verification Community Together

DVCon Japan 2025 logoWelcome Message from the DVCon Japan 2025 General Chair

Dear friends,
DVCon Japan 2025 will be held on August 20, 2025 in Shinagawa, Tokyo.

DVCon (Design and Verification Conference) is mainly sponsored by Accellera Systems Initiative. DVCon focuses on solving problems in a wide range of areas such as logic design, architecture study, functional verification, HW/SW co-verification, analog simulation, functional safety compliance, security verification, and application of AI to development flow in semiconductors and systems, DVCon is the premier conference for learning and discussing best practices in the application of IEEE and Accellera standard languages, formats, and methodologies.

DVCon has been held in the U.S. for more than 30 years and has been held in Japan since 2022, with online and on-demand delivery in 2022 and in-person in 2023 and 2024. We were able to offer a diverse and in-depth program with a variety of paper presentations, tutorial sessions, and exhibits from sponsors and exhibitors. We would like to thank all the audiences, presenters, sponsors, and all those involved.

DVCon Japan 2025 will be held at a venue that is only a 3-minute walk from the Takanawa Exit of Shinagawa Station. The morning sessions will consist of general sessions and panel discussions, and the afternoon will be technical sessions including many paper presentations and tutorials. DVCon is a forum for sharing and discussing the latest information in a wide variety of areas including functional verification strategies, SystemVerilog, UVM, UPF, SystemC, PSS, formal verification methodologies, HLS, AMS, IP-XACT, and more, and discussion in a wide variety of fields. It is also a great opportunity to meet and mingle with other attendees, presenters and attendees, sponsors, and Accellera representatives.

We encourage designers, engineers, and managers to attend. We look forward to seeing you there. Finally, I would like to take this opportunity to thank our Gold and Silver sponsors and supporters for their support of the event, as well as the Information Processing Society of Japan and IEEE CEDA AJJC for their sponsorship.

Genichi Tanaka
DVCon Japan 2025 General Chair

The DVCon Japan 2025 Call for Paper Submissions is open through May 31.

For more information, visit the DVCon Japan website.

Welcome to the Third Edition of DVCon Taiwan

DVCon Taiwan 2025 logoWelcome Message from the DVCon Taiwan 2025 General Chair

On behalf of the DVCon Taiwan 2025 steering committee, it is my honor to welcome you all to the third edition of the Design and Verification Conference in Taiwan.

The first DVCon Taiwan was successfully held in 2023, and DVCon Taiwan 2024 was another milestone. DVCon Taiwan 2025 will be held at Hsinchu Lakeshore Hotel. We encourage students, professors, engineers, and managers to attend.

We’re thrilled to have you join us for what promises to be an exciting and productive conference. This year, we have assembled a lineup of renowned speakers, insightful presentations, and engaging exhibits to foster collaboration and knowledge sharing. We hope you take advantage of this opportunity to connect with attendees, exchange ideas, and gain valuable insights.

Finally, I would like to take this opportunity to thank our sponsors and supporters for their contributions to the event, as well as Taiwan IC Design Society for their sponsorship.

We look forward to a successful DVCon Taiwan 2025!

For more information on DVCon Taiwan, visit dvcontaiwan.org.

Robert Chen
DVCon Taiwan 2025 General Chair

DVCon India Marks a Decade of Innovation in Design and Verification

DVCon India 2025 logoWelcome Message from the DVCon India 2025 General Chair

On behalf of the DVCon India 2025 steering committee, it is my great pleasure to welcome you all to the 10th edition of the Design and Verification Conference in India, set to take place on September 11-12, 2025, in Bangalore, India. As we mark this momentous milestone, we continue to embrace our theme, “Architecture to Analytics – A2A”, highlighting the evolving landscape of semiconductors.

Building on the success of last year, we will continue with our dedicated focus groups covering System & IP Modeling, Architecture & Design, RISC-V, Analog & Mixed-Signal Verification, and Post-Silicon Validation. These focus areas foster meaningful dialogue and strengthen cross-industry collaboration to drive innovation in semiconductor design and verification.

We extend an open invitation to the entire semiconductor design and verification community to participate, collaborate, and contribute to DVCon India 2025. Your expertise, passion, and insights will play a pivotal role in making this conference a grand success.

Let’s celebrate a decade of DVCon India, fuel the spirit of Designnovation, and drive breakthroughs from Architecture to Analytics!

Pradeep Salla
DVCon India 2025 General Chair

The Call for Panels, Workshops, and Tutorials is open through May 30, 2025. Visit the DVCon India 2025 resource center for more information.

Explore the Future of Design and Verification at DVCon Europe

DVCon Europe 2025 logoJoin the design and verification community at DVCon Europe 2025, taking place October 14-15 at the Holiday Inn Munich City Center in Munich, Germany. This year’s conference will feature an insightful keynote “We Didn't Start the Fire…Open Source Software in 2025,” presented by Amanda Brock, CEO of OpenUK. There will also be dynamic panel discussions, 16 in-depth tutorials, and a wide array of technical paper presentations. Attendees will also have the opportunity to explore the latest innovations in tools, IP, and services from leading providers in the exhibition area. For program updates and registration details, visit the DVCon Europe website.

The Call for Research Papers is open through June 30.

SystemC Evolution Day

SystemC Evolution Day logoCo-located with DVCon Europe, the 10th annual SystemC Evolution Day will take place on October 16 at the Holiday Inn Munich City Centre. This full-day, in-person workshop is dedicated to the ongoing advancement of the SystemC ecosystem through the evolution of its standards. The event features a series of focused sessions covering current challenges and forward-looking topics in SystemC standardization and development.

The program is in development. For the latest updates, visit the SystemC Events page.

To explore past workshops and access a wide range of SystemC resources, visit the SystemC.org community portal.

 

Recent Event Summaries

DVCon China 2025

DVCon China 2025 logoThe recent DVCon China 2025 conference, held on April 16 at the Shanghai Renaissance Pudong Hotel, brought together industry leaders, engineers, and researchers to discuss the latest advancements in electronic design automation (EDA) and verification methodologies. Key Highlights of the conference included:

  • Focus on Artificial Intelligence (AI): AI was a central theme, with keynote speeches and technical sessions exploring its impact on chip design and verification. Chuck Alpert from Cadence discussed "Unlocking the Power of Agentic AI in Chip Design," emphasizing how AI can revolutionize verification processes. Thomas Li of Synopsys addressed the emergence of AI factories and their implications for multi-die design and verification. Pei-Hsin Ho from UniVista Industrial Software Group presented a vision for collaborative efforts between human experts, generative AI, and EDA engines in RTL design and verification.
  • Advancements in Verification Methodologies: The conference showcased the application of standardized languages and tools, such as SystemC, SystemVerilog, and the Universal Verification Methodology (UVM), in modern verification processes. Discussions also covered the use of SystemVerilog Assertions (SVA) and the Property Specification Language (PSL) to enhance verification efficiency.

For more information on the conference proceedings and future events, visit the DVCon China website.

SystemC Evolution Fika logoHighlights of the March 2025 SystemC Evolution Fika

The latest SystemC Evolution Fika brought together experts and developers to discuss advancements in SystemC modeling, tooling, and standardization. Key topics included:

  • TLMBoy: A Game Boy Emulator in SystemC TLM-2.0
  • DRAMSys: Exploring DRAM Design Spaces
  • SystemC Reporting API Enhancements
  • SystemC 4 Proposal: Hierarchy and Connectivity Exploration
  • SystemC Summer of Code 2025

For more details and to access presentation materials and recordings, visit the SystemC Evolution Fika events page.

Record Attendance and Industry Momentum Highlight DVCon U.S. 2025

DVCon U.S. 2025 logo"DVCon U.S. 2025 was a tremendous success, bringing together the brightest minds in design and verification to explore the latest advancements in AI, formal verification, and industry standards,” stated Tom Fitzpatrick, DVCon U.S. 2025 General Chair. “With attendance reaching a new record since returning in-person, the enthusiasm and engagement from our attendees, speakers, and exhibitors showcased the vibrant innovation driving our industry forward. From thought-provoking keynotes to informative and educational technical sessions and a dynamic exhibition floor, this year’s conference reaffirmed DVCon’s role as the premier event for the design and verification community. We’re excited to be moving to a new venue in 2026, giving the conference room to grow and continue delivering an exceptional experience for our community."

Participants from 32 countries, representing approximately 350 companies, attended DVCon U.S. 2025, including 404 first-time attendees. The event featured 32 sponsors and exhibitors, six of whom were making their debut. Overall attendance reached approximately 1,067, including representatives from 26 exhibiting companies. The exhibit floor was sold out.

DVCon U.S. 2026 will be held March 2-5 at the Hyatt Regency in Santa Clara, California. Xiaolin Chen is General Chair for DVCon U.S. 2026.

The proceedings from DVCon U.S. 2025 will be available in June. To view proceedings from past conferences, visit the DVCon archives site.

 

Accellera in the News

Barry Pangrle, a power architect, recently published an article, “An Inside Look at UPF 4.0” in Semiconductor Engineering, offering a detailed exploration of the evolution of the standard and the key benefits introduced in its latest release.

Paul McLellan, editor for EDAGraffiti.com, also covered the latest UPF 4.0 standard in his article, “1801-2024 IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems.”  His coverage highlights key advancements in power intent specification and verification introduced in this latest update to the IEEE 1801 standard.

At DVCon U.S. 2025, Bernard Murphy joined Accellera’s Portable Stimulus workshop, which highlighted the latest developments in the PSS 3.0 standard. He also attended our luncheon featuring insightful presentations on the newly released UVM-MS 1.0 and the emerging Federated Simulation standard, along with the announcement of this year’s Technical Excellence Award. Check out his recap, “Accellera at DVCon 2025: Updates and Behavioral Coverage,” now available on SemiWiki.com.

 

More Resources

Access to Hundreds of Accellera Videos

Find the latest videos from our working groups, industry events and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

Explore the DVCon Archives

For papers, posters, presentations and videos from our DVCon conferences around the globe, visit the DVCon archive site.

 

IEEE GET Program Update

Since its inception, the Accellera-sponsored IEEE GET Program has resulted in over 212,000 downloads. The most recent addition is the IEEE Std. 1801™-2024 Unified Power Format (UPF) 4.0 Standard. The IEEE GET Program provides engineers and chip designers worldwide with no-cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

Accellera Global Sponsors

CadenceSiemens EDASynopsys

Contact us if you are interested in becoming a Global Sponsor.

 

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