Community Newsletter: July 2020


  • Message from the Chair
    • Accellera is adapting and rising to the challenge!
  • Join us Online at the 57th Design Automation Conference
    • Lunch break panel of experts focused on Functional Safety
    • Tutorial on IP Security Assurance and why it’s important
  • Conferences Throughout the Year
    • DVCon Europe is going virtual
    • SystemC Evolution Day 2020 will be a full-day online event
    • DVCon U.S. 2020 wrap-up
    • DVCon U.S. 2020 available to all on demand, including Accellera Day videos
    • Mark your Calendars: DVCon U.S. 2021 will go virtual
    • Due to the pandemic, DVCon China and DVCon India were cancelled for 2020
  • Working Group Updates
    • UVM 2017-1.1 Reference Implementation now available
    • SystemC Verification Working Group releases updates to the UVM-SystemC Library
    • SystemC AMS User Guide and examples now available
    • IEEE Get Program Update – 110K downloads!


Message from the Chair

Lu Dai, Accellera Systems Initiative Chair“Change alone is eternal, perpetual, immortal.” - Arthur Schopenhauer

As we wrap up our 32nd annual DVCon conference, we say goodbye to our friends at MP Associates. We have enjoyed a relationship spanning 30 years and at least 40 DVCons throughout the U.S., India, and Europe. In addition to our DVCons around the globe, MPA has been a valuable contributor to many industry conferences over the years, including the Design Automation Conference (DAC). We thank them for their many decades of conference management services as well as the many relationships forged over the years.

I would like to extend a warm welcome to Conference Catalysts. We look forward to working with the new team on our upcoming DVCon Europe 2020 and DVCon U.S. 2021 conferences. Conference Catalysts also provides conference management services for other industry organizations such as the IEEE, the IEEE Sensors Council, and International Society of Information Fusion, to name just a few.

Our DVCons, like conferences everywhere, are evolving because of the pandemic. We’ve made the decision to hold DVCon Europe as a virtual conference this year. It follows our DVCon U.S. 2020 conference, recently made available as a virtual offering to those that were unable to attend in person earlier this year. DVCon U.S. 2021 will also be held as a virtual conference in March, ensuring that all who would like to attend can make their plans well ahead of time.

We are also looking forward to our participation in the virtual DAC this year with a panel focused on Functional Safety and an IP Track session focused on our emerging IP Security Assurance standard.

Accellera is adapting and rising to the challenges of the current climate. Our working group activities have continued to make progress and advance. We have several releases recently available or coming later this year, including Portable Test and Stimulus 1.1, the UVM 2020-1.0 Reference Implementation, SystemC-UVM 1.0beta3, and the SystemC-AMS 2.3 User Guide.

It has been fascinating to see the new possibilities and opportunities that continue to develop as a result of a nearly universal virtual working environment. Our Functional Safety Working Group will have a Whitepaper ready later this year, the UVM-AMS Working Group is developing a Design Objective Document, and the IP Security Assurance Working Group will provide an updated Whitepaper. We have also added eight new Associate Members to our roster: AEDVICES, ams AG, Arteris, ClioSoft, COSEDA, Defacto, Marvell and SiFive.

Winston Churchill said it best, “To improve is to change; to be perfect is to change often.”

We look forward to seeing you online at our events and connecting with you through our forums.

Lu Dai, Accellera Systems Initiative Chair


Join us Online at the 57th Design Automation Conference (DAC)

Accellera’s Functional Safety Working Group Addresses Standardization Efforts to Improve Automation, Interoperability, and Traceability

Thursday, July 23

We invite you to join us for our virtual lunch break at DAC focused on Functional Safety. The mission of our recently formed Functional Safety Working Group (FSWG) is to develop a standard to provide a comprehensive and unified definition of the Functional Safety intent to improve automation, interoperability, and traceability across the Functional Safety development lifecycle of electronic circuits and systems.

Join us as we present an overview of the scope, needs, and goals defined by the FSWG including developments since its formation. Introductions by Lu Dai, Accellera’s Chair, Martin Barnasconi, Technical Committee Chair, and Alessandra Nardi, FSWG Chair, are followed by several informative presentations by functional safety experts focusing on specific perspectives, challenges, and opportunities. You have an opportunity at the end of the presentations to ask questions of the participants during a live Q&A session. Speakers include Bala Chavali, RAS Architect - Principal Member of Technical Staff, AMD; Ghani Kanawati, Technical Director of Functional Safety, Arm; Jyotika Athavale, Principal Engineer and Lead Platform Technologist, Intel; Franck Galtié, Director Automotive Functional Safety, NXP Semiconductors; and Riccardo Vincelli, Director of Functional Safety Competence Center, Renesas.

For more information, visit here. For the link to the session on the DAC website, visit here.

The lunch break session is free, but registration through DAC is required to attend. You can register for “I Love DAC” with no fees.

“Why Care About IP Security Assurance – What Could go Wrong?”

Tuesday, July 21

Organized by IPSA Working Group Chair Brent Sherman, this IP Track Session will discuss Accellera’s emerging IP Security Assurance standard aimed at addressing security concerns in IP. It will also provide a discussion on third-party IP security risks associated with FPGA bitstream integration and key learnings from an IP supplier performing security assurance.

Registration with the Design Automation Conference is required to attend this presentation. Find out more about this session here.


Accellera Conferences Throughout the Year

DVCon Europe 2020 Goes Virtual

DVCon Europe 2020The seventh annual DVCon Europe 2020 is being transformed into a virtual event to be held October 27 & 28.

The conference will include virtual papers, tutorials and panels with industry experts sharing best practices on system-level engineering and embedded software, advanced verification and validation, IP reuse and design automation, functional safety and security, and mixed-signal and low-power design and verification. Special interest areas are artificial intelligence, hardware/software co-design, RISC-V, next generation automotive, and 5G.

There will be two keynote speakers: Victoria (Vicki) Mitchell, Vice President Systems Engineering at Arm, will present “The Benefits of Hardware DevOps,” and Dr. Matthias Traub, Head of Architecture and Technologies at Volkswagen, will give the keynote “Hardware/Software Codesign for Automotive Electronics – A Paradigm Shift.”

“We are very pleased to have Vicki and Matthias on board. Both keynotes fit perfectly with our ambition to further strengthen the collaboration and interaction between software, hardware, and system-level experts, and jointly develop the standards and methodologies required to design and verify the products of the future,” stated Joachim Geishauser, General Chair of DVCon Europe.

For more information on the conference please visit the website.

To view the papers and presentations from DVCon Europe 2019, visit here.

SystemC Evolution Day 2020 Goes Virtual

SystemC Evolution Day 2020The fifth annual SystemC Evolution Day will be held virtually on October 29 following the virtual DVCon Europe conference. The online gathering of the SystemC community will include interesting technical presentations and creative discussions and debates to advance the standard. The details of how the full-day workshop will be run are still evolving, so please continue visit the website for updated information.

For more information about SystemC Evolution Day 2020 and to view past presentations, visit here.

DVCon U.S. 2020 Wrap-up

DVCon U.S. 2020The 32nd annual DVCon U.S. was just beginning as COVID-19 was becoming a concern in the United States. To accommodate the cancellation of some of the presentations as a result of the rapidly changing environment, the steering committee was able to compress the schedule and fill the gaps. Attendees were able to enjoy an engaging full technical program over the course of three days instead of the traditional four.

On the opening day of the conference, traditionally known as Accellera Day, Accellera offered attendees a full morning tutorial focused on the Portable Test and Stimulus Standard (PSS) and what users could look forward to with the upcoming PSS 1.1. The tutorial was followed by an Accellera-sponsored luncheon that began with an update by Accellera Chair Lu Dai, followed by an introduction to the Functional Safety Working Group presented by Technical Committee Chair Martin Barnasconi. Philipp A. Hartmann was honored during the luncheon with the Accellera 2020 Technical Excellence Award for his many contributions to the advancement of the SystemC language standard.

The afternoon was filled with short workshops including two sponsored by Accellera—one focused on the IP Security Assurance Standard and another on HLS and SystemC.

DVCon U.S. 2020 Available to All On-Demand

DVCon U.S. 2020To honor the work that all session, tutorial, poster, short workshop, and panel presenters put into the conference, and to connect with registered attendees who were unable to participate in person, the DVCon U.S. Steering Committee created a virtual DVCon U.S. 2020 event now available to the public through August 14, 2020.

“I’m thrilled that we are continuing the 2020 program online with many of the presentations that were unable to be presented during the live conference,” stated Vanessa Cooper, DVCon U.S. Technical Program Committee Chair. "Due to the rapidly evolving environment at the onset of the conference, we were able to pivot the live program quickly and compress if from four days to three, but that still left many without the benefit of the informative technical material. I’d like to thank the technical program committee for continuing its efforts and coordinating with the presenters to record some of their papers, posters, tutorials and short workshops for this on-demand experience.”

Please visit the DVCon U.S. 2020 virtual conference website for program details and to access the virtual conference.

The Accellera-sponsored videos from Accellera Day are now available to view and download from the DVCon U.S. 2020 virtual website:

  1. Tutorial: “Portable Stimulus: What’s Coming in 1.1 and What it Means for You
  2. Luncheon panel: “The Portable Stimulus Standard
  3. Short Workshop: “An Introduction to the IP Security Assurance Standard
  4. Short Workshop: “How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity

DVCon U.S. 2021 is Going Virtual

The Steering Committee is planning an exciting virtual DVCon U.S. that will begin March 1, 2021. Stay tuned for more information and the Call for Contributions coming soon.

DVCon China & DVCon India

Due to the pandemic, our DVCons in India and China were cancelled for 2020. We will continue to provide updates as we find new ways to continue to reach these regions and the users of Accellera standards around the globe.


Working Group Updates

UVM 2017-1.1 Reference Implementation Now Available!

UVM - Universal Verification Methodology

The UVM 2017-1.1 release is now available for download. The latest version of the Reference Implementation addresses changes that resulted from clarifications from the IEEE, including the behavior of print operations and transaction recording. The release also corrects a bit-shifting error in the uvm_reg_map, cleans up comments and general code, and adds missing accessors to the register field API.

For more information on the Universal Verification Methodology (UVM) Working Group, including a list of quick links and resources, please visit the working group page. If you’d like to comment or have questions, please visit the UVM Community Forum discussions.

SystemC Verification Working Group (VWG) Releases Updates to the UVM-SystemC Library


The SystemC VWG recently released the beta3 version of the proof-of-concept implementation for the Universal Verification Methodology based on the SystemC language standard (UVM-SystemC) for public review. This release contains an updated UVM-SystemC Language Reference Manual as well as compatibility updates to work with SystemC up to version 2.3.3. The well-known UBus verification example has been added to the latest release, and memory management issues have been fixed. For more information on the UVM-SystemC library, as well as a list of resources, visit the SystemC VWG page.

SystemC AMS User Guide and Examples Now Available


The SystemC Analog/Mixed-Signal (AMS) Working Group has released the application examples documented in the SystemC AMS User’s Guide, which was made available earlier this year. The user’s guide and examples are compatible with the IEEE 1666.1 SystemC AMS standard. The material is available for download at the SystemC AMS download page. Please contact your local EDA tool provider to find out if they support SystemC AMS simulations. Find more information on the community page in the section “Simulation environments,” or contact the experts through the SystemC AMS forum.

IEEE Get Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 110,000 downloads. The IEEE Get Program provides no-cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.



2020 Global Sponsors

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Copyright 2020 Accellera Systems Initiative