Community Newsletter: September 2018
IN THIS ISSUE:
- Message from the Chair
It’s been a busy summer at Accellera with much to be proud of
- DVCon Europe
General Chair Martin Barnasconi provides highlights of the upcoming conference
- SystemC Evolution Day
Chair Joachim Geishauser gives insights into the full-day workshop
- Accellera Day India
Portable Stimulus and UVM are the focus of this full-day event
- DVCon U.S.
Save the date! The 2019 conference and exhibition will be Feb 25-28, 2019
- SystemC Synthesis
Working Group Chair Andres Takach looks for input on datatypes
- UVM Tutorial
Technical tutorial now available online
- In the News
New IP Security Assurance Working Group; Congratulations Martin Barnasconi, 2018 Leadership Award recipient; Portable Test and Stimulus Standard 1.0 now available
We’ve had a very busy summer season at Accellera. It began with the Design Automation Conference in San Francisco where we had our annual breakfast with presentations from our working group leaders, followed by the announcement of our new standard, Portable Test and Stimulus Standard (PSS) 1.0. We also recently announced the formation of the new IP Security Assurance Working Group, and we’ve been planning for three events coming this fall: DVCon Europe, SystemC Evolution Day, and Accellera Day India.
We are very proud of the work the team has done on PSS. Many member companies had products ready to support the new standard when it was announced, demonstrating its importance to the user community. The Portable Stimulus Working Group is continuing to build upon the 1.0 standard and is working hard on the next revision based on user feedback.
The IP Security Assurance Working Group was just approved by the Accellera Board of Directors at the end of August and already has more than 20 companies participating including silicon providers, IP suppliers and EDA vendors. There is great momentum in this new working group, and it’s an exciting time to be a part of it.
We are always looking for participation in our working groups, especially when they are new and there is great opportunity to help shape the direction they will take. New ideas on ways we could improve our engineering efficiency and quality through the standardization process are especially welcome. Our community forums are an excellent place to propose improvements or provide feedback, as well as be a resource for the latest information on our standards.
Our fall events are just around the corner. DVCon Europe and SystemC Evolution Day are co-located in Munich this October, and Accellera Day India will be an exciting full-day event in November with in-depth training on Portable Stimulus and UVM.
We are looking forward to seeing you this fall at one of our events!
Lu Dai, Accellera Systems Initiative Chair
The 5th edition of DVCon Europe will take place on October 24 and 25 in Munich, Germany. Technical experts from around the world will come together to share the latest developments and experiences on the application of EDA languages, methodologies, and tools for the design and verification of electronic systems and integrated circuits.
If you aren’t already familiar with DVCon Europe and how it can benefit you, I encourage you to read the blog by Thomas Klotz, conference Vice Chair, explaining the 5W’s: Who-What-When-Where-and-Why.
We will have a strong and diverse technical program this year including tutorials, panels, keynotes, presentations, and an attractive exhibition. Both days start with an exciting keynote speech. On Wednesday, Stefan Jockusch, Siemens PLM Software Inc., will present the keynote, “Driving Digitization with a Boundary Free Innovation Platform,” and on Thursday, Philippe Magarshack from ST Microelectronics will present the keynote.
The first day is packed with many tutorials. I invite you to read the blog from Oliver Bell, Tutorial Chair, which gives a good summary of the tutorial program. DVCon Europe also includes a strong industry panel. Paul Nottingham, Panel Chair, shares more insights on the panel.
The technical program is available online and covers technical papers, tutorials, and panels. This year we’ve included the paper abstracts in the online program to help you to plan your personal conference schedule. The highlights of the technical program are presented by Alexander Rath, Technical Program Chair.
A special co-located event this year is SystemC Evolution Day, which will take place the day before DVCon Europe on October 23. Joachim Geishauser, SystemC Evolution Chair, explains the importance of system-level design and standardization in his blog.
As you can see, the DVCon Europe program is stronger than ever! We are looking forward to seeing you on October 23-25 in Munich!
System Level First – YES! For the first time, SystemC Evolution Day is happening at the same location as the very successful Design and Verification Conference and Exhibition (DVCon) Europe. SystemC Evolution Day is happening the day before DVCon Europe 2018 on Tuesday, October 23 at the Holiday Inn Munich City Centre Hotel, as a co-located event focusing on Accellera’s SystemC standardization efforts.
System Level First – System-level exploration is the first step in developing new products. For this process step, a modeling environment needs to be in place to make this happen. In times of ever growing complexity, the reuse of building blocks is essential to make such system level exploration happen in the given timeframe and budget. Therefore, an environment based on standards is key to enable the creation of an industry ecosystem around this. In its third year after a very successful first edition in May of 2016, SystemC Evolution Day is intended to advance the SystemC standards with a full-day technical workshop.
System Level First – First, a well-defined standard is required. As part of international standards evolution, living standards need feedback from the user community to adopt to new requirements and improve usability. SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together the experts from the SystemC user community.
We look forward to seeing you at the SystemC Evolution Day and DVCon Europe 2018!
We are looking forward to bringing you Accellera Day India this November in Bangalore. The full-day in-depth technical program will be held on November 14, 2018 at the Radisson Blu Bengaluru. The format will be similar to the very successful Accellera Day held each year at DVCon U.S. We’ll have a tutorial exploring the new Portable Stimulus standard in the morning that will focus on a set of typical design use cases from a variety of applications. It will show how to use the Portable Test and Stimulus Standard to create abstract models of verification intent and will show how the models can be reused and leveraged from project to project.
In the afternoon we will have a tutorial on UVM that will introduce engineers to the new reference implementation aligned with IEEE 1800.2 and created by the Accellera UVM Working Group. Engineers attending this informative tutorial will learn the steps they need to take to update their verification components to be IEEE-compatible.
The organizing committee has put together an exciting, information-packed day. For more information on the program, visit our event page. Registration is open, so please join us for this unique event to learn about the latest advances in Portable Stimulus and UVM. We look forward to seeing you in Bangalore in November!
Save the date! DVCon U.S. 2019 will be held February 25-28, 2019 at the DoubleTree Hotel in San Jose, California.
"We have an outstanding steering committee in place to develop a compelling program for the 2019 DVCon U.S. conference, which will be highly technical and continue the tradition of making DVCon a ‘must-attend’ conference for practicing design and verification engineers and their managers,” stated Aparna Dey, DVCon U.S. 2019 General Chair.
by Working Group Chair Andres Takach
The SystemC Synthesis Working Group is very active and is currently addressing several issues, including:
- Defining more clearly what elaboration behavior is supported for synthesis. More specifically, the dynamic module instantiation, binding, and naming, (e.g., using loops during elaboration).
- Considering what array/vector container to support.
- Looking at the use of C++ 11 attributes for synthesis directives.
- Analyzing the inclusion of AC datatypes as a numerical library.
Our goal over the next 12 months is to see some convergence on a second version of the SystemC Synthesis standard with the issues resolved and based on more updated versions of the C++ standard such as C++ 11, 14, and possibly 17. At SystemC Evolution Day last October there were some datatype proposals presented, and we’d like to get more feedback from the community on them. We have set up a new SystemC Datatypes forum where you can provide suggestions and input. We look forward to hearing from you.
The DVCon U.S. 2018 tutorial, “IEEE-Compatible UVM Reference Implementation and Verification Components,” is now available online (registration is required). This in-depth technical tutorial introduces viewers to the new reference implementation aligned with IEEE 1800.2 and created by the Accellera UVM Working Group. The speakers use the new reference implementation to describe the new features and changes relative to UVM 1.2. Viewers will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples help viewers gain the practical knowledge they need to adopt the IEEE 1800.2™ Standard for UVM.
New IP Security Assurance Working Group! Accellera recently announced the formation of the IP Security Assurance Working Group (IPSA WG). The charter of the new working group is to provide a security assurance standard for hardware IP and its associated components to address security risks when integrated into embedded systems. To find out more about the IPSA WG read the press release or visit the IPSA WG page. If you are not already an Accellera member and are interested in joining to participate in the working group, find out how to join.
Congratulations Martin Barnasconi, recipient of the 2018 Accellera Leadership Award. The award was presented to Martin at the 55th Design Automation Conference (DAC) during the Accellera Breakfast and Technical Panel. The award recognizes the vision, leadership, and contribution to standards development, governance, and promotional activities of an Accellera member on behalf of the organization. Martin was honored for his dedication to the advancement of the SystemC ecosystem and growth of standards dissemination in Europe. For more information about Martin’s tremendous contributions read the press release.
Portable Test and Stimulus Standard 1.0 is now available for free download. The Portable Test and Stimulus Standard (PSS) defines a specification to create a single representation of stimulus and test scenarios usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of a scenario that run on a variety of execution platforms, including, but not necessarily limited to, simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can specify a set of behaviors once and observe consistent behavior across multiple implementations. For more information including release notes, tutorials and the press release, Accellera’s Portable Stimulus Community is a good resource for the latest information available on the new standard.
2018 Global Sponsors
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Copyright 2018 Accellera Systems Initiative