SystemC Evolution Day 2016SystemC Evolution Day 2016

Workshop on the Evolution of SystemC-related Standards
Tuesday, May 3, 2016
Munich, Germany

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Enthusiastic SystemC User Community Joins Forces at First SystemC Evolution Day

As a result of the high level of interest in the SystemC birds-of-a-feather session at DVCon Europe 2015, the SystemC user community met again earlier this month for a full day to discuss the evolution of the various SystemC standards. With more than 50 participants, the new Accellera-sponsored technical workshop was sold out, with representatives from more than 20 companies and seven universities in attendance.

SystemC Evolution Day 2016

The main objective of the SystemC Evolution Day was to identify the areas to align and accelerate the different SystemC standardization initiatives within Accellera and propose solutions for standards inclusion. The workshop started with presentations covering user experiences and standardization proposals in the fields of high-level synthesis, parallel SystemC simulation, transaction-level modeling (TLM) and interactive tracing and debug. In the afternoon, various technical sessions focused on the interaction between multiple SystemC working groups addressing C++11/14 standard adoption, multi-threaded SystemC, TLM for serial interfaces and UVM-SystemC combined with Configuration Control and Inspection (CCI). In a wrap-up session, the main conclusions were shared, including proposals for further standardization. The material and presentations are available for Accellera members active in any of the SystemC working groups.

The participants were all very excited to actively contribute to the success of this workshop. After the positive feedback from the attendees, the organization committee is exploring the best and most effective way to continue the workshop on a regular basis. 


Summary of May 3, 2016 Event

The first SystemC Evolution Day was a new full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem.  In several in-depth sessions, selected current and future standardization topics around SystemC were discussed in order to accelerate their progress for inclusion in Accellera and IEEE standards.

The SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together the experts from the SystemC user community and the Accellera working groups to advance SystemC-related standards in a full day workshop.

2016 Location: Intel Deutschland, Am Campeon 10, 85579 Neubiberg, Munich, Germany

Date: May 3, 2016

Time: 10:00 a.m. – 06:00 p.m.

This event was free of charge

For more information contact: This email address is being protected from spambots. You need JavaScript enabled to view it.

Organization Team

  • Philipp A Hartmann, Intel
  • Oliver Bell, Intel,
  • Martin Barnasconi, NXP
  • Matthias Bauer, Infineon



Welcome, Introduction, SystemC WG Updates

10:45 – 12:45

Lightning talks
Presentation and discussion of smaller contributions & needs

  • Addressing the HLS Coding Barrier
  • Seven Obstacles in the Way of Parallel SystemC Simulation
  • Events and Timing in TLM - Extend and Clarify
  • Tracing and Interactive Test/Debug in SystemC and SystemC AMS


Lunch break*

13:45 – 15:15

#1.1 SystemC/TLM and Language Standards (C++11/14)

#2.1 TLM Standard for Serial Interfaces


Coffee break*

15:45 – 17:15

#1.2 Multi-Threaded SystemC and External Interfaces

#2.2 UVM-SystemC & Configuration, Control and Inspection (CCI)


Coffee break*

17:45 – 18:30

Wrap-up, next standardization steps, closing

19:30 – 21:30

Dinner (optional, self-paid)

* Lunch and breaks sponsored by Accellera. Must be registered to receive a lunch voucher.

Lightning Talks

In the morning a series of lightning talks are presented covering concrete, but smaller, standardization proposals as well as introducing new standardization needs around SystemC. For each of these short presentations, time for an interactive discussion will be included to gather feedback and support and for identifying the next steps towards standardization.

Addressing the HLS Coding Barrier

Dominik Strasser, OneSpin Solutions

The verification of code for HLS is an important SystemC application. By working with HLS customers in the formal verification area, a number of inconsistencies in the standard have emerged, which require non-standard solutions on a synthesis tool-by-tool basis. These include simulation-synthesis mismatches, differing number formats and others, reminiscent of the early RTL synthesis days. OneSpin would like to present its findings at the event and discuss how we might resolve these synthesis coding style issues, to enable more general verification tools to be applied in different synthesis flows.

Seven Obstacles in the Way of Parallel SystemC Simulation

Rainer Doemer, UC Irvine

The IEEE 1666‐2011 standard defines SystemC based on discrete event simulation and sequential co-routine semantics, despite explicit parallelism in the model and ample parallel processor cores available in today’s host computers. In order to evolve the SystemC standard towards faster parallel discrete event simulation, substantial hurdles must be overcome. This presentation identifies seven obstacles in the standard that stand in the way of efficient parallel SystemC simulation, including the co‐operative multitasking semantics, the role of channels, TLM‐2.0, sequential modeling mindset, and technical details. For each obstacle, we discuss the problem and propose a potential solution toward truly parallel SystemC.

Events and Timing in TLM – Extend and Clarify

Jakob Engblom, Intel Corporation

We propose a small addition to the TLM features of SystemC, a payload-enhanced event class, along with a mechanism that will let active initiators serve events to passive devices without involving the kernel, inside their own temporal decoupling time slice.  By having a payload in the event, it is possible to write certain types of TLM code in a more natural way.  By allowing one module to defer the execution of events to another module, more efficient scheduling of event-driven code and more consistent temporal decoupling semantics are made possible – at the cost of putting more responsibility on the initiators.

Tracing and Interactive Test/Debug in SystemC and SystemC AMS

Karsten Einwich, COSEDA Technologies

This presentation aims to initiate the discussion, whether the SystemC and SystemC-AMS tracing should/can be unified. The more flexible tracing infrastructure in SystemC AMS adds extended tracing capabilities around user-defined data type support as well as advanced control of the tracing during the simulation. Additionally, the SystemC AMS working group currently discusses to integrate an interactive debug feature, allowing to read/write/listen to values in the SystemC model in a consistent way. This feature can be generalized and should be make available for SystemC as well.

Technical Sessions

In the afternoon, technical in-depth sessions on ongoing standardization topics are held with a special focus on areas with overlap between multiple SystemC Working Groups. The following sessions are planned:

#1.1 SystemC/TLM and Language Standards (C++11/14)

Moderator: Ralph Görgen, OFFIS

The evolution of the C++ language – more specific: the new standards C++11 and C++14 – have introduced a number of features that can significantly improve quality, safety and performance. In this session, it is planned to discuss and evaluate how these features can be used efficiently by SystemC and TLM designers and methodology library providers and how they can leveraged to improve design productivity, model quality and simulation performance. This includes the exploration of possible extensions of the core SystemC languages for improved C++11 integration and the consequences for the underlying standards.

#1.2 Multi-Threaded SystemC and External Interfaces

Moderator: Mark Burton, GreenSocs

There has been much research in the area of multi-threading SystemC, both at the level of processes and threads and at the level of models themselves, both automatic and co-operative. In this topic, we welcome contributions about how SystemC itself can be made more parallel, and how multi-threaded models can be deployed in SystemC. As it is closely related, we also welcome contributions that explore the integration of external simulators and models into SystemC, especially where those simulators are themselves multi-threaded. The eventual aim of this topic will be to propose additions to the language which will facilitate multi-threading as well as interfaces to foreign simulation environments that will support multi-threading.

#2.1 TLM Standard for Serial Interfaces

Moderator: Martin Schnieringer, Bosch

TLM 2.0 as part of IEEE 1666-2011 is a well-defined and widely deployed abstraction level for on-chip memory mapped components connected via buses and interconnects, enabling quick platform assembly. For common (automotive) serial protocols such as SPI, CAN, FlexRay, I2C, etc., no such modeling is established yet, resulting in additional integration effort of various ad-hoc solutions from different sources. In this session, ongoing activities in that area are presented and discussed, including requirements and scenarios that shall be supported by such a standard for TLM Serial Interfaces. Additionally, the potential reuse of existing TLM 2.0 components such as interfaces, sockets, phases, payloads etc. and missing elements required for allowing easy and intuitive modeling of serial interfaces will be explored.

#2.2 UVM-SystemC & Configuration, Control and Inspection (CCI)

Moderator: Martin Barnasconi, NXP

Accellera’s Universal Verification Methodology (UVM), originally developed in SystemVerilog, is now made available in SystemC to facilitate the creation and reuse of system-level verification components and environments. The UVM-SystemC library offers dedicated verification functionality such as fine-grained simulation phases, factory overrides, configuration management, register model, and test and stimuli control. In parallel, the SystemC Configuration, Control and Inspection (CCI) standard is under development for the exchange of information between the design under verification (DUV) and tooling. The objective of this session is to align and unite the proposed methods for the DUV register configuration and control, from a test bench and tools perspective.

After the technical sessions, a dedicated wrap-up slot will be used to present the main results from the different in-depth discussions, summarizing next steps for further progressing these topics within the relevant Accellera SystemC Working Groups by the Accellera members. If you would like to become an Accellera member to participate in the working groups, information on how to join can be found at