Accellera Day at DVCon U.S.
Accellera Systems Initiative invites you to a special day dedicated to technical standards at the 2017 Design and Verification Conference U.S. in San Jose, CA. Find out the latest in technologies that you can apply immediately and those that will help to define the future. Join us at this day-long event to connect with experts and users as we learn, share, and network on the latest in standards innovations!
Monday, February 27, 2017
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Full Day Tutorials
- Creating Portable Stimulus Models with the Upcoming Accellera Standard
The first version of the Accellera Portable Test and Stimulus Standard (PSS) is nearing completion. This timely tutorial presents an introduction to the standard’s main features leveraging a series of usage examples defined by PSWG members that represent many of the common challenges faced in today’s multi-core designs. The tutorial will show with actual coding examples how the verification and portability challenges of these examples are met using the standard.
- Introducing IEEE 1800.2 – The Next Step for UVM
From inception to today, UVM has swept through project teams worldwide which makes it ready for the next step with the IEEE. The IEEE 1800 committee is completing the work on UVM as the 1800.2 standard. This rigorous review of the Accellera work has resulted in some changes that improve UVM as a standard for interoperability. As we review these changes, we will also examine the impact it will have on your existing verification environments including how to debug and regold those environments improving your ability to share verification IP among globalized teams.
- SystemC Design and Verification – Solidifying the Abstraction Above RTL
We will focus on three key components that could help you make that decision: design, modeling, and testbench. We'll start by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration. A discussion of modeling for high-performance simulation will follow to complete our view of the overall design. Of course, we need to verify this fast-running design with a testbench approach that can be reused at RTL so we'll discuss how to apply the emerging UVM-SystemC standard.
All attendees of the Monday tutorials are invited to our Accellera-sponsored luncheon. Accellera will present the 2017 Technical Excellence award and provide a look forward to the worldwide DVCon events, latest news, and working group activities. Next, a town hall meeting will cover such topics as: follow-up questions from the Portable Stimulus morning tutorial, future directions for the UVM Working Group, and the lastest activity in the SystemC working groups.
DVCon Expo and Booth Crawl
You won't want to miss the annual DVCon Booth Crawl on the exhibit floor featuring cocktails and conversations in a casual environment with the DVCon exhibitors. Mingle from booth to booth while enjoying food and drinks provided by exhibitors.
DVCon U.S. 2017
February 27 - March 2, 2017
San Jose, CA
April 19, 2017
Parkyard Hotel Shanghai
Registration open | Advance rates until March 17
Accellera Verification and System Level Design Forum
April 21, 2017
Find out more >
Event Dates Announced
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- Accellera Standards Technical Update video presentation
- System-Level Modeling for Today and Tomorrow with SystemC video presentation
- SCE-MI 2.3 released. Download | Read the press release
- New Portable Stimulus Working Group
- Tom Alsop (of Intel) Named Accellera Systems Initiative 2017 Technical Excellence Award Recipient
February 22nd, 2017
- Accellera Day Opens DVCon U.S. on Monday, February 27 with Three Timely Tutorials
February 22nd, 2017
- Lu Dai of Qualcomm Elected Chair of the Board of Accellera
February 13th, 2017