Universal Verification Methodology

UVM - Universal Verification Methodology

Universal Verification Methodology (UVM) is a standard to enable guaranteed development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. Accellera provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).

  • Validated on multiple simulators
  • Scales from block to system level
  • Enhanced for multi-language verification
  • Standardized as UVM 1.2


UVM Resources

UVM Panel Discussion

This panel from DAC 2014 featured a UVM 1.2 Roundtable with John Aynsley, CTO of Doulos, who engaged panelists Rich Newton, Ericsson, Amol Bhinge, Freescale, Colin McKellar, Imagination, and Mohamed Elmalaki, Intel in a lively discussion on UVM usage, migration planning and potential future enhancements. Listen to the UVM 1.2 roundtable discussion >

UVM News

The class reference document UVM 1.2 for SoC verification is now available. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. New features include enhanced messaging and improvements to the register layer. UVM 1.2 and its reference implementation are available for download. The implementation includes detailed release notes and script to help users upgrade, as some new features introduce backward incompatibility.

UVM 1.2 is proceeding to IEEE standardization. Find out more >

Join the IEEE P1800.2 Working Group. First meeting is August 6, 2015. Register for this meeting or find out more >

UVM has an active user community. The LinkedIn group tops 6,400 members.

Found a bug or a have an enhancement request? Find instructions for reporting to the UVM Mantis Database here.