Community Newsletter: August 2026

IN THIS ISSUE:

• Message from the Chair
• Reports from DAC luncheon Panel, “Embracing AI for Advanced Design & Verification”
• More Media Coverage: Creating a Common Language for Functional Safety Blog
• What's New in PSS? PSS 3.1 Public Review Coming Soon!
• Learning PSS Video Series Available on YouTube
• Upcoming Events
  • Submission Deadline Fast Approaching for DVCon U.S. 2027
  • DVCon India Taking Place Next Week
  • DVCon Japan September 10
  • DVCon Europe Announces Keynotes
  • SystemC Evolution Day – Save the Date!
• More Resources
  • DVCon U.S. 2026 Presentations Now Available on Archives Site
  • Hundreds of Videos Available On-Demand on Accellera’s YouTube Channel
  • IEEE Program – Download Standards Fee Free

 

Message from the Chair

TBD

 

 

 

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

AI, EDA & Standards Take Center Stage at Accellera’s DAC Luncheon and in the Press

Accellera's luncheon at last month's 63rd Design Automation Conference (DAC), "Embracing AI for Advanced Design and Verification," drew nearly 100 attendees for a lively discussion about how AI is changing semiconductor design and verification, and the role standards can play as the technology becomes more deeply integrated into EDA workflows.

Moderated by Mike Gianfagna, SemiWiki, the panel featured Dr. Jiang Hu, IEEE Fellow and Eric Rubin Professor at Texas A&M University; David Zhi LuoZhang, co-founder and CEO of Bronco AI; and Simon Davidmann, AI+EDA Researcher. The panelists explored emerging challenges around interoperability, data exchange, APIs, workflow integration, trust, privacy, benchmarking, and reproducibility. They also looked ahead to the growing use of agentic AI and more autonomous, goal-driven workflows that could fundamentally change how design and verification are performed.

Audience participation added another dimension to the discussion. Attendees responded in real time to a live online quiz about how they are using AI, where they see the greatest benefits, where Accellera standards could have the most impact, and their biggest concerns about AI adoption. The results reinforced many of the panel's observations, including the importance of standards to enable AI integration and the critical issue of trust.

The luncheon and its forward-looking discussion have since been highlighted in two industry articles. In SemiWiki's "DAC 2026: Accellera Luncheon Panel on Embracing AI for Advanced Design and Verification," moderator Mike Gianfagna provides a detailed recap of the panel and audience responses, highlighting the potential need for standards around data formats, Python-based APIs and knowledge exchange as AI-driven workflows evolve.

Electronics Weekly's Caroline Hayes takes a closer look at the panelists' perspectives in "Standards and AI will shape-shift EDA," exploring how AI may drive new approaches to interoperability, workflows, governance and benchmarking while accelerating the move toward agentic design and verification.

The large turnout, engaged audience participation, and continued industry coverage underscore the importance of the conversation as AI increasingly influences the future of electronic design automation.

 

Additional Media Coverage – Creating a Common Language for Functional Safety

By Alessandra Nardi, Functional Safety PWG Chair

In a recent Semiconductor Engineering blog, Alessandra Nardi, Chair of Accellera's Functional Safety Working Group, discusses why the semiconductor industry needs a standardized way to represent and exchange functional safety information.

As designs and supply chains become increasingly complex, safety data is often spread across spreadsheets, proprietary databases, custom scripts, and tool-specific formats, creating challenges with interoperability, traceability, and automation. Accellera's Functional Safety Language (FSL) is being developed to address this gap by providing a common language and data model for functional safety information, initially focusing on FMEDA.

Nardi explains how FSL can help connect safety information across EDA tools, suppliers, IP providers, semiconductor companies, and system integrators, while providing a foundation for greater automation and future AI-assisted workflows.

Check out her blog "Why the Semiconductor Industry Needs A Common Language For Functional Safety" in Semiconductor Engineering.

 

What’s Next for Portable Stimulus? PSS 3.1 Public Review Coming Soon!

The Portable Stimulus Standard (PSS) 3.1 Draft Standard will soon be available for public review, giving the design and verification community an opportunity to review the latest enhancements to PSS and provide feedback before its release.

PSS 3.1 is a focused release that builds on the capabilities of PSS 3.0, with updates concentrated in four key areas:

• A stronger constraint language – Enhancements that provide greater flexibility and control when defining constraints.
• More reusable libraries – Improvements that make it easier to create practical, reusable PSS libraries that can be shared across projects and teams.
• Greater control over generated target code – New capabilities that give models more control over what is produced for target implementations.
• Address spaces and registers – Updates that close gaps and strengthen modeling capabilities in the address and register layer.

The public review will provide an opportunity for the industry to evaluate the specification and provide feedback before it is finalized. The Portable Stimulus Working Group invites comments and feedback through its Community Forum.

Watch Accellera's Drafts Under Public Review page in the coming weeks for the PSS 3.1 draft and details on the public review period. For more information about PSS and the development of the standard, visit the Portable Stimulus Working Group page.

 

The "Learning PSS" Journey Continues: Nine Sessions Now Available!

Accellera's "Learning PSS" video series continues to grow, with nine sessions now available. Presented by Tom Fitzpatrick, PSS expert and charter member of the Accellera Portable Stimulus Working Group, the educational series introduces the Portable Stimulus Standard (PSS), progressing from fundamental concepts to techniques for building reusable, scalable verification models.

The series begins with an introduction to PSS and the verification reuse and portability challenges it addresses, then builds on those fundamentals with sessions covering data types, actions and activities, communication, components and pools, code organization, and constraints. Along the way, viewers learn how PSS supports horizontal and vertical reuse, data and control flow, object-oriented inheritance and type extensions, and greater control over generated verification scenarios.

Whether you're new to PSS or looking to expand your expertise, you can watch the first nine sessions at your own pace in the "Learning PSS" playlist on Accellera's YouTube channel.

More to come, so stay tuned as the series continues. For more information about PSS, including a list of resources, visit the Portable Stimulus Working Group page.

 

Upcoming Events

DVCon U.S. 2027 Submission Deadline is Fast Approaching!

There's still time to be part of the DVCon U.S. 2027 technical program, but the deadline is quickly approaching! Extended abstracts are being accepted through September 7, 2026, and the deadline will not be extended.

Engineers, researchers, and practitioners are invited to submit extended abstracts showcasing innovative methodologies, practical applications, and real-world experiences in the design and verification of electronic systems and integrated circuits. Topics include functional verification, safety-critical systems, low-power design, machine learning and AI, design and verification reuse, mixed-signal methodologies, hardware/software co-verification, Portable Stimulus applications, and more.

Proposals for sponsored workshops and tutorials are also being accepted, providing additional opportunities to share expertise and engage with the design and verification community. These proposals are also due no later than September 7, 2026.

DVCon U.S. 2027 will take place March 1–4, 2027, at the Hyatt Regency Santa Clara in Santa Clara, California. Don't miss your opportunity to contribute to one of the industry's premier technical conferences for design and verification professionals.

Additional details, including submission guidelines, are available on the DVCon U.S. 2027 website.

DVCon India 2026 Brings the Design and Verification Community Together in Bengaluru

DVCon India 2026 will take place next week, September 1–3, at the Radisson Blu, Marathahalli in Bengaluru. Expanding to three full days this year, the conference will bring together design and verification professionals for keynotes, technical sessions, panels, tutorials, workshops, networking, and an exhibition focused on the latest advances in electronic design and verification.

Accellera will have a strong presence on the opening day of the conference, with three presentations:

• CDC-RDC Verification Standard 1.0 for Interoperable Abstract Model
• What's Cooking in SystemC 4.0 and Federated Simulation? Let's Be Friends
• Portable Stimulus Standard: Examples and What's Next

The broader DVCon India program will explore many of the technologies shaping the future of design and verification, including AI-driven design and verification, formal verification, advanced system and IP-level design, and emerging methodologies. Learn more about the program and register on the DVCon India website.

DVCon Japan 2026 Comes to Yokohama September 10

DVCon Japan 2026 will take place September 10 at Pacifico Yokohama North, bringing together design and verification professionals for a full day of keynotes, technical presentations, tutorials, panel discussions, exhibits, and networking.

The program will kick off with a keynote, "AI Physics X Agentic AI," presented by Masaya Ogushi, Senior Solution Architect at NVIDIA, exploring the use of AI and accelerated computing across semiconductor design and manufacturing. The technical program will cover a broad range of topics, including AI, SystemC, functional verification, hardware security, and advanced design and verification methodologies.

Accellera standards will also be well-represented throughout the program. Sessions include:

• Accellera SystemVerilog Mixed-Signal Interface Birds of a Feather
• SystemC/SystemC AMS: Virtual Prototyping for Complex Heterogenous Systems
• Effective Description Techniques in SystemVerilog
• CDC-RDC Verification Standard 1.0 for Interoperable Abstract Model

Visit the DVCon Japan 2026 website to explore the full program and register to attend.

DVCon Europe 2026 Announces Keynotes and Opens Registration

DVCon Europe 2026 will take place November 17–18 at the Holiday Inn Munich in Munich, Germany, bringing together the European design and verification community for two days of keynote presentations, technical sessions, tutorials, panel discussions, networking, and an exhibition.

This year's keynote speakers will address two timely challenges facing the industry. Professor Hussam Amrouch, Technical University of Munich, will present "AI for Chips, Chips for AI — and the Growing Talent Gap in Between." He will explore the two-way relationship between AI and semiconductors—from AI chips enabling more efficient training and inference to the growing role of AI in designing increasingly complex chips—and discuss the critical need to develop the next generation of engineering talent.

Antoine Madec, Director of Verification at Axelera AI, will present "Perfection Is a Bad Idea: Pragmatic Verification of Complex ASICs at a Scale-Up." Drawing on his experience developing complex ASICs, Madec will examine how verification teams can make practical trade-offs among complexity, time-to-market, and available resources while focusing effort where it delivers the greatest value.

Registration is now open, with reduced rates available through October 18. Visit the DVCon Europe website for registration information, program updates, and the latest conference news.

Save the Date for the 11th Annual SystemC Evolution Day

Mark your calendar for SystemC Evolution Day on November 19, 2026, immediately following DVCon Europe in Munich, Germany. This full-day technical workshop brings together the SystemC user community, industry experts, and Accellera Working Groups to discuss the evolution of SystemC standards and help shape the future of the SystemC ecosystem.

Through in-depth technical sessions and collaborative discussions, participants will explore current and emerging standardization topics and share ideas that can help advance future Accellera and IEEE standards. It's a unique opportunity to engage directly with the experts driving SystemC development and contribute to its future direction.

Watch for additional program details coming soon. For the latest information on SystemC Evolution Day and other SystemC activities, visit the SystemC community portal at systemc.org.

 

More Resources

DVCon U.S. 2026 Presentations Now Available on Archives Site!

Proceedings from DVCon U.S. 2026, held in Santa Clara in March, are now available for download. For proceedings from all our DVCon conferences, visit the DVCon Archive site.

Explore Hundreds of Accellera and DVCon Videos On-Demand

Find the latest videos from our working groups, industry events, and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

IEEE GET Program – Download Standards at No Cost

The IEEE GET Program provides engineers and chip designers worldwide with no cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

Accellera Global Sponsors

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