Accellera at the 53rd Design Automation Conference
Tuesday, June 7, 2016
7:30am - 9:00am
Austin Convention Center, Room 9C
Registration is now closed - event is sold out
UVM, the Universal Verification Methodology, has experienced enormous success in its first 5 years. It's used by thousands of engineers worldwide in nearly all digital verification flows. The IEEE P1800.2 committee is diligently working to standardize UVM. But what’s next for UVM? Future possibilities include UVM multi-language, UVM for mixed-signal, and UVM for acceleration. Accellera is also in the late stages of bringing a native SystemC implementation of UVM to the community. Join us to discuss what more should be considered for UVM.
At the Accellera DAC breakfast this year, we will assemble a presentation and panel to discuss the next 5 years for UVM. We'll provide an update on the IEEE P1800.2 UVM standard efforts and then discuss the future with a panel of verification experts. They will shed light on the technical challenges the industry is still facing and how UVM could further evolve to address the needs in areas like SoC verification and software-driven verification.
Moderator: Tom Alsop, Principal Engineer, Intel
- Mark Glasser, Principal Verification Engineer, NVIDIA
- Warren Stapleton, Sr. Fellow, AMD
- Jonathan Bromley, Verification Consultant, Verilab
- Faris Khundakjie, Sr. Technical Lead in Server Tools Flows and Methods, Scalable Performance Development Group, Intel
So come join us and start your day at DAC with an Accellera update by Accellera Chair Shishpal Rawat, the presentation of the Accellera Leadership Award, and a view to the future of UVM. The breakfast is free to all DAC attendees, but registration is required.
Portable Stimulus Tutorial
“How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges”
Monday, June 6
Austin Convention Center, Room 15
The upcoming Accellera portable test and stimulus standard specification will permit the creation of a reusable model for a variety of users across different levels of integration under different configurations. This tutorial will outline a set of common usage examples that emphasize specific verification, reuse, and portability challenges. Verification challenges include randomization of both data and control flow. Reuse challenges include migrating tests from IP level to SoC. Portability challenges include growing test to improve coverage when running on faster platforms and executing at the full platform speed. Finally, the tutorial will show how portable stimulus can address the usage examples.
This panel is organized by Tom Anderson of Breker Verification Systems, Inc. and Larry Melling of Cadence Design Systems, Inc. Registration with the Design Automation Conference is required to attend the tutorial. Find out more >
Birds of a Feather Meeting
“Next Generation Unified Verification Requirements (UCIS 2.0)”
Tuesday, June 7
7:00pm - 8:30pm
Austin Convention Center, Room 12AB
The Accellera Unified Coverage Interoperability Standard (UCIS) brings together much needed coverage information from Simulation, Formal and Emulation tools from multiple vendors. This standard is undergoing a revival right now, and the committee is seeking input from the industry at large to drive a comprehensive coverage solution to unify verification flows. Now is the time to influence the direction of this work!