Community Newsletter: August 2012

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Message from Accellera Systems Initiative Chair

Shishpal Rawat, Accellera Systems Initiative ChairThings are heating up this summer at Accellera Systems Initiative. We’ve started on new standards efforts and have in-depth presentations and tutorials for you. We also have new leadership in some of our continuing efforts. IP-XACT has a new leader, Christian Fraisse of STMicroelectronics; Verilog AMS welcomes Scott Little of Intel as its new chair.

We have embarked on the next generation of standards with SystemRDL (Specification for Register Description Language). SystemRDL is designed to increase productivity, quality and reuse during the design and development of complex digital systems. SystemRDL 1.0 is available for download, and the SystemRDL working group, led by Oren Katzir of Intel, is active and engaged. Join now!

We have just released the entire tutorial series from the 2012 Design and Verification Conference. Featuring in-depth technical presentations given by experts in their field, this is your number one resource to find the latest in standards including SystemC, UVM, UCIS and IP-XACT. Online tutorials are available at no cost on our media site. While there, check out other available videos and user presentations.

At the Design Automation Conference in June, we debuted UCIS (Unified Coverage Interoperability Standard), a first step towards the creation of an API that allows for interoperability of verification coverage data across multiple tools from multiple vendors. A new User Forum for UCIS has been established for help, contributions and general discussion. The North American SystemC Users Group also held their eighteenth meeting, and presentations are now available.

We were honored by Synopsys with the Tenzing Norgay Interoperability Achievement Award. And, we honored vice chairman Dennis Brophy with our first ever leadership award for his outstanding work in bringing Accellera and the Open SystemC Initiative together to forge our new organization.

In July, we announced a new SystemC library update. The proof-of-concept library is compatible with the IEEE 1666-2011 Standard (which is available at no charge via the Accellera Systems Initiative-sponsored GET IEEE program). Download the proof of concept library now under open source license (login required).

We hope you are enjoying your summer. If you have any comments or suggestions for us, please contact us. And check our website often for information on ongoing standards activities.

Shishpal Rawat, Chair


Technical Committee Spotlight: New SystemC Library Now Available


Accellera Systems Initiative announces the release of version 2.3.0 of its SystemC open source proof-of-concept library, now available at no charge to the worldwide electronic design community. Compatible with the newly revised IEEE 1666 "Standard SystemC Language Reference Manual," announced by the IEEE Standards Association in November 2011, version 2.3.0 provides a number of important new features, including support for transaction-level modeling (TLM), a critical approach to enable high level and more efficient design of complex ICs and SoCs in a single library.

Read more >


Tutorials from DVCon 2012 Now Online

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. A featured part of the conference consists of tutorials that have a high level of interest and offer strong educational content. Tutorials from DVCon 2012 are now available at no cost to users worldwide on the Accellera Systems Initiative media site.

Featured tutorials include:

  • An Introduction to IEEE 1666-2011, the New SystemC Standard


This tutorial represents a unique chance to improve your understanding of SystemC and give you a kick start with the new language standard. Topics taught in detail include:

  • New process control extensions to SystemC, which provide more flexibility when using SystemC to model abstract schedulers and abstract clock gating, unify the old thread and clocked thread constructs, and give more flexibility when using SystemC for hardware synthesis.
  • New constructs that give more flexibility and control when pausing and restarting the scheduler.
  • The new sc_vector class, which has powerful mechanisms for coding regular structures.
  • New features that facilitate the use of SystemC with multiple operating system threads, paving the way to exploiting multicore architectures for SystemC simulation.
  • Other technical enhancements to SystemC, including event lists, named events, filtering reports based on verbosity, and control over the number of processes that can write to a signal.
  • Enhancements to TLM-2.0 that permit more flexible use of the generic payload attributes.

Presented by John Aynsley, Doulos; David C. Black, Doulos; and Tor Jeremiassen, Texas Instruments.

Watch now >

  • Verification and Automation Improvement Using IP-XACT

IP-XACTThis tutorial focuses on providing an opportunity to learn more about IP-XACT and how this standard can be used to enhance your IP based design and verification flow.

Presented by John Swanson, Synopsys; Kamlesh Pathak, STMicroelectronics; David Murray, Duolog Technologies; and Sylvain Duvillard, Magillem Design Services.

Watch now >

  • UVM: Ready, Set, Deploy!

UVMPresented by expert verification methodology architects and engineers, the tutorial begins with an introduction to UVM (Universal Verification Methodology), with concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. The tutorial continues with the UVM register package, including how to create and manage stimulus and checking at the register level.

Presented by Tom Fitzpatrick, Mentor Graphics; John Aynsley, Doulos; Kathleen Meade, Cadence Design Systems; Adiel Khan, Synopsys; Vanessa Cooper, Verilab; Stephen D'Onofrio, Paradigm Works; Peter J. D'Antonio, The MITRE Corp.; John Fowler, AMD; Justin Refice, AMD; and Mark Strickland, Cisco System.

Watch now >

  • An Introduction to the Unified Coverage Interoperability Standard

The Unified Coverage Interoperability Standard (UCIS) is a new Accellera standard for an application programming interface (API) that facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors. This tutorial provides an overview of UCIS and its API and how users plan to enhance their verification flows using it.

Presented by co-chairs of the UCIS Technical Committee: Dr. Richard Ho, D. E. Shaw Research and Dr. Ambar Sarkar, Paradigm Works, Inc.

Watch now >

Accellera Systems Initiative Honored with 2012 Tenzing Norgay Interoperability Achievement Award from Synopsys 

Shishpal Rawat receives Tensington Norgay award on behalf of Accellera Systems InitiativeAccellera Systems Initiative has received Synopsys' twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. Accellera Systems Initiative was formed in December 2011 through the merger of the Open SystemC Initiative (OSCI) and Accellera. Since 2000, the two organizations have developed standards that are widely used in the semiconductor industry; Accellera developed SystemVerilog, Unified Power Format (UPF) and IP-XACT; OSCI developed SystemC and TLM-2.0.

Read more >


Dennis Brophy Receives First Annual Leadership Award

Dennis Brophy receives leadership award from Shishpal RawatDennis Brophy is the first recipient of the Accellera Systems Initiative Leadership Award. The Award recognizes the vision, leadership and contribution to standards development, governance and promotional activities of the organization. "Dennis has been very active in defining direction for Accellera's standards activities for more than two decades," remarked Shishpal Rawat, Accellera Systems Initiative chair. "As one of the longest serving board members, Dennis has helped shape Accellera into the premier standards development organization for the EDA and IP industry."

Read more >


Event Roundup

SystemCNorth American SystemC Users Group Meeting

Presentations are now available for the NASCUG XVIII meeting. The meeting was co-located with the Design Automation Conference 2012 (DAC) in San Francisco, California.

Find out more >


SystemCEuropean SystemC Users Group Meeting

Tuesday, September 18, 2012
Co-Located with FDL '12 in Vienna, Austria

Find out more >


DVCon 2013DVCon 2013

February 25-28, 2013
DoubleTree Hotel, San Jose, CA

2013 Call for Abstracts now underway >

Watch a brief video retrospective of the 2012 conference >


Thanks to our Global Sponsors
for their support of NASCUG and the video tutorial production



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