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Community Newsletter: August 2017


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative Chair

If you attended DAC in June, I hope you were able to join us for one of our activities. We enjoyed a great turnout at our annual breakfast where we presented Shishpal Rawat with the Accellera Leadership Award and held a Town Hall discussion on our emerging Portable Stimulus standard. A panel of experts were on hand to answer many intriguing questions from the audience. We also held Birds-of-a-Feather meetings for the Multi-Language Verification Working Group and the Unified Coverage Interoperability Standard (UCIS) Working Group, and members of our Portable Stimulus Working Group presented an in-depth tutorial as part of the DAC program. We also held our first DVCon Japan at the end of June in Shin-Yokohama. The full day conference attracted engineers from around the region eager to participate in the expansion of what had previously been known as SystemC Japan.

Our working groups continue to be very active this summer. Among them, SystemRDL 2.0 is on target for rollout in the fourth quarter; UCIS is ramping up activity and would like your participation, especially from those in the user community to help ensure the success of this interoperability standard; and the Portable Stimulus Early Adopter Release is in public review. We encourage participation in the new Portable Stimulus forum so that your input and feedback can be addressed ahead of the 1.0 release. Look for an interview with Faris Khundakjie, the Chair of the Working Group, in our next newsletter to give insight into what can be expected in the first release and what will follow.

We have three conferences to look forward to this fall: DVCon India, DVCon Europe and SystemC Evolution Day. We hope you will join us at these informative events. It is your participation and collaboration that are key to their success.

Your input in our forums is also very important. Sharing your experiences with our standards, asking questions and providing feedback is essential to the evolution of our standards. And as always, we welcome you to join Accellera and participate in our working groups — it’s the best way to make sure your voice is heard.

I look forward to seeing you at one of our conferences in the fall. Enjoy the rest of your summer!

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

DVCon India 2017DVCon India 2017

DVCon India is a must-attend conference dedicated to design and verification of IPs, SoCs and electronic systems. The conference provides an excellent platform for attendees to discuss, network and contribute to the standards, flows and methodologies enabling silicon product realization.

Every year strong and dedicated committee members are identified and they work relentlessly to come up with a two-day packed agenda covering keynotes from industry luminaries, tutorials from experts not restricted to EDA companies, panel discussions with leaders, papers and posters from the fraternity. The first day of the conference features Opening Talks and a Lamp Lighting Ceremony, followed by keynotes: “Industry’s Next Challenge: The Software Gap,” presented by Christopher Tice, Synopsys; “Re-emergence of Artificial Intelligence Based on Deep Learning Algorithm,” presented by Vishal Dhupar, NVIDIA Corporation; and “Would You Send Your Child To School In An Autonomous Car?” presented by Apurva Kalia, Cadence. Friday morning will have two keynote talks:  “Innovations in Computing, Networking, and Communications: Driving the Next Big Wave in Verification,” presented by Ravi Subramanian, Mentor, A Siemens Business; and “Disruptive Technology that will Transform the Auto Industry,” presented by Sanjay Gupta, NXP India Pvt. Ltd.

As in previous years, the conference provides two parallel tracks: ESL and Design & Verification (DV). The ESL track is targeted toward the adoption of SystemC in the semiconductor industry, and the DV track provides a platform for engineers to share experiences and best practices on design and verification. Attendees are free to choose between the two tracks based on the topics of interest and learn what’s next at the exhibitor stalls. Both days provide multiple opportunities to network and connect with the peers in the industry. With a track record of more than 600 experts representing 80+ organizations from all over the world, DVCon India is a unique conference for all members of the semiconductor ecosystem.

Register for DVCon India >

 

DVCon Europe 2017DVCon Europe 2017

Message from DVCon Europe General Chair Oliver Bell

I’m pleased to welcome you to the 2017 edition of the Design and Verification Conference & Exhibition Europe to be held October 16-17, 2017.

This year’s DVCon Europe continues its tradition with a great lineup, with both days packed with tutorials, panels, keynotes, technical presentations, and an attractive exhibition. Each day will begin with a keynote held by a prominent Industry speaker.

Mr. Horst Symanzik from Bosch Sensortech will kick off DVCon on Monday with his keynote “Consumer MEMS Products: Quality rather than Commodity,” an overview about some of the challenges in the ASIC development for current and future MEMS products and how to tackle these challenges while originating from a mixed-signal heritage.

The focus on Monday during the day will be on Tutorials, and we’ll introduce an evening reception at the extended DVCon Europe Exhibition, which includes well-established EDA players and a thriving number of emerging companies.

On Tuesday, Mr. Berthold Hellenthal from Audi will present "Driving Virtual Prototyping of Automotive Electronics."  Berthold will highlight ongoing developments and challenges for the increased usage of Virtual Prototypes at the automotive domain, as cars are transforming into mobile datacenters with onboard sensors and parallel computing.

DVCon Europe keynotes, papers, presentations and panels unite the practical application of state-of-the-art design and verification techniques. You will see them applied at a broad mixture of different domains, such as automotive, Internet of Things, Industry 4.0, or wireless systems toward 5G. Primary areas of the program include System Level, Virtual Prototyping, Advanced Verification with UVM and Formal, Design for Functional Safety, IP Reuse, Mixed-Signal and Low Power Techniques.

The conference will also give you the opportunity to meet and connect with the DVCon community, which includes experts from different companies, fields and countries, design automation tool users and vendors, senior fellows and freshmen, as wells as researchers and many more.  

At this time, many volunteers across the DVCon community including authors, presenters, reviewers and steering team members are working hard to shape an interesting and quality program. It’s amazing for me to see this fantastic collaboration happening throughout the industry.

Oliver Bell, General Chair, DVCon Europe 2016Adjacent to DVCon Europe, we will have also the 2nd edition of Accellera’s SystemC Evolution Day, following its successful launch last year. This “spinoff” from DVCon Europe will take place October 18th at the Technical University of Munich.  

Registration is just opening, so don’t wait to reserve your seat and join the DVCon Europe community. I am looking forward to meeting you in downtown Munich in October!

 

SystemC Evolution Day 2017

Message from the SystemC Evolution Day Organization team: Philipp A Hartmann, Intel; Oliver Bell, Intel; Martin Barnasconi, NXP; Matthias Bauer, Infineon; Thomas Kruse, Infineon

SystemC Evolution Day 2017After the successful SystemC Evolution Day last year, preparations are ongoing for a second SystemC Evolution Day this year. Our goal is to have fruitful discussions with SystemC users about the further development of the language. SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together the experts from the SystemC user community and the Accellera working groups to advance SystemC standards in a full-day workshop.

This year, four in-depth technical sessions are planned to discuss new ideas and look over suggestions. The first topic will be checkpointing in SystemC, a useful feature of computer system simulators. The goals of this session are to discuss how such a feature can be implemented and to get input from the language design, modeling, tool building, and user communities on checkpointing for SystemC.

A second topic will deal with the possible standardization around registers. Different organizations have different register modeling libraries, and different users will certainly have different experiences and requirements. During this session, some of the proposals for standardization around registers will be presented. There will also be time to discuss the direct feedback from the user community.

In the third session, the current challenges around the existing SystemC datatypes will be discussed. The dedicated SystemC datatypes working group is looking for feedback and help from the community on the different potential paths forward to improve the datatypes semantics and performance in the future.

Last, but not least, the fourth topic is on throughput-accurate modeling and synthesis of abstract interfaces in the context of high-level synthesis. This topic is currently not addressed in the SystemC synthesis standard. The planned discussion aims to explore approaches that could lead to proposals for expanding the synthesis standard in that area.

After the technical sessions, the Accellera members will hold an open discussion session. In the first part, they will summarize the next steps within the relevant Accellera SystemC Working Groups. In the second part, they will summarize open items brought up during the closing discussion.

SystemC Evolution Day 2017 is planned for October 18, 2017 (one day after DVCon Europe 2017) from 8:30am to 5:00pm. It will be located at the Technical University of Munich (Arcisstraße 21, 80333 Munich, building 9, 2nd floor, room 2999).

View detailed agenda and register >

 

DVCon U.S. 2018DVCon U.S. 2018

Save the date!  DVCon U.S. will be held February 26 - March 1, 2018 at the DoubleTree Hotel in San Jose, CA.

"DVCon U.S., now in its 30th year, continues to be the 'must-attend' conference for practicing design and verification engineers and engineering management," stated Dennis Brophy, DVCon U.S. 2018 General Chair. "The DVCon U.S. Steering Committee crafts the industry's most compelling technical program from solicited ideas on conference panels, papers, poster sessions, tutorials and workshops. It brings EDA tool suppliers and users together to share practical information and methods that can be immediately applied to their electronic system design and verification challenges."

Important dates: The deadline for extended abstracts has been extended to August 18, 2017. Tutorial proposals and panel proposals are due September 29, 2017.

 

DVCon China 2018DVCon China 2018

Proceedings are now available from the inaugural DVCon China, held in April. DVCon China 2018 will be held April 19, 2018 at the Doubletree by Hilton Shanghai-Pudong. The Steering Committee has been assembled and Jinnan Huang will serve as General Chair.

 

Portable Stimulus

Portable Stimulus Early Adopter Release Public Review

The Early Adopter version of the new Portable Stimulus Specification is available for Public Review through September 15th, 2017. The Portable Stimulus Working Group is actively seeking public feedback on the specification. Questions, comments and suggestions can be posted on the Accellera Portable Stimulus Community Forum. The specification can be downloaded here.

The Early Adopter specification provides a comprehensive explanation of the new Portable Stimulus Domain Specific language. This declarative language is designed for abstract behavioral description using actions; their inputs, outputs and resource dependencies; and their composition into use cases including data and control flows. These use cases capture test intent that can be analyzed to produce a wide range of possible legal scenarios for multiple execution platforms (e.g., virtual platforms, simulation, emulation, prototypes, silicon, etc.). There is also a semantically-equivalent C++ Class Library to specify the same declarative abstract behavior descriptions in an environment that may be more comfortable to some users. The Early Adopter specification also includes a preliminary mechanism to capture the programmer’s view of a peripheral device, independent of the underlying platform, further enhancing portability.

What would you like to know about Portable Stimulus?

  • Why portable stimulus?
  • What problem does it solve?
  • How does PSS relate to UVM? Will it become part of UVM?
  • What is the value of PSS?
  • What can I do in PSS that can’t be done in existing languages?

We encourage you to visit the Portable Stimulus Forum to post your questions and become part of the discussion. With the Portable Stimulus Specification in Public Review, the Portable Stimulus Working Group is in the process of gathering feedback. Your input is important! Also consider joining the working group to make your voice heard.

Portable Stimulus: The Making of a Standard

Gabe Moretti, an Accellera Co-Founder, interviews the Working Group Chair and Vice Chair on the evolution of the Portable Stimulus standard

The Accellera-sponsored DVCon U.S. 2017 covered, among many other topics, the work on the Portable Stimulus proposed standard. I took the opportunity to interview the leaders of the Accellera Working Group (WG) that is developing it: Faris Khundakjie, leading technologist at Intel and Chair of the WG and Tom Fitzpatrick, Verification Technologist, Design Verification & Test Division at Mentor Graphics, the WG Vice Chair.

Moretti: What is the purpose of Portable Stimulus? What problem does it solve?

Read interview >

Portable Stimulus Webinar 3-Part Series Available Online

If you missed our webinar series, “Creating Portable Stimulus Models with the Upcoming Accellera Standard” based on the DVCon U.S. 2017 tutorial, you can view it on demand. The series is divided into three parts: 1) Portable Stimulus: The Next Leap in Verification & Validation Productivity and Introducing Portable Stimulus Concepts & Constructs; 2) Building System-Level Scenarios and Generating Tests from Portable Stimulus; and 3) Coverage in Portable Stimulus, The Hardware/Software Interface Library, and What’s Next for Portable Stimulus.

 

New SystemC Tutorial Available

SystemCPresented at DVCon U.S. 2017, the tutorial "SystemC Design and Verification – Solidifying the Abstraction above RTL" focuses on three key components that could help you make the decision toward using SystemC as the primary point of entry above RTL: design, modeling, and testbench. It starts by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration. A discussion of modeling for high-performance simulation follows. Finally, the tutorial discusses how to apply the emerging UVM-SystemC standard to verify your fast-running SystemC design with a testbench approach that can be reused at RTL. View the tutorial >

 

Accellera in the News

Shishpal Rawat, Recipient of the 2017 Accellera Leadership AwardCongratulations Shishpal Rawat, recipient of the 2017 Accellera Leadership Award. The award was presented at the Design Automation Conference during the Accellera breakfast and town hall meeting on Tuesday, June 20.

Shishpal became chair of Accellera in June, 2010. As chair of Accellera, he oversaw the consolidation of standards bodies, namely the merger with OSCI, as well as the acquisition of the OCP standard. He also helped to extend the relationship with the IEEE Standards Association’s IEEE Get Program for an additional 10 years, ensuring continued public access to view and download current EDA standards at no charge, courtesy of Accellera. Find out more >

IEEE 1800.2 for UVM is now available for download at no charge under the Accellera-sponsored IEEE Get Program.

 

 

2017 Global Sponsors

CadenceMentor GraphicsSynopsys

Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.

 

Copyright 2017 Accellera Systems Initiative