Community Newsletter: February 2016
IN THIS ISSUE:
- Message from the Chair
An exciting year ahead
- Accellera Day at DVCon U.S.
A day filled with updates and insights
- DVCon U.S.
An information-packed 4-day technical program
- Save the Dates!
DVCon India and DVCon Europe announce dates and locations
- Technical Spotlight
UVM-SystemC public review
As we look forward to another exciting and productive year at Accellera, 2016 is already in full swing. The Portable Stimulus Working Group is currently evaluating contributions to assist in defining a portable test and stimulus specification language that can be used to generate stimulus throughout the design process. The SystemC Verification Working Group (VWG) is well underway developing a new UVM-SystemC Library containing a Language Reference Manual and proof-of-concept implementation that will be compatible with the Accellera SystemC 2.3.1 library. An early version was released in December 2015 to solicit feedback from the public.
We will also be extending our relationship with the IEEE Standards Association’s IEEE Get Program whereby the public has access to view and download current EDA standards at no charge courtesy of Accellera. We’ve benefited immensely from our relationship of over 13 years with IEEE-SA and look forward to continuing it for many more.
And later this month we will have the first of our annual global DVCon Conferences with Accellera Day opening DVCon U.S. on February 29th. We plan to offer a full day of informative technical tutorials to our attendees and honor our Technical Excellence Award recipient during our luncheon. This annual award was established to recognize the outstanding achievements of an individual among our working group members and their significant contributions to the development of Accellera standards.
We look forward to working with you to evolve platforms on which the electronics industry can collaborate to innovate and deliver global EDA standards. We welcome all of our new members who joined the Accellera community recently to contribute to our working groups and standards.
See you at DVCon U.S. 2016!
Shishpal Rawat, Accellera Systems Initiative Chair
Accellera invites you to join us as we open DVCon U.S. with a day filled with insights into technologies that you can apply immediately and those that will help to define the future.
- Tutorial 1: Preparing for IEEE UVM Plus UVM Tips and Tricks
- Tutorial 2: SVA Advanced Topics: SVAUnit and Assertions for Formal
12:00pm-1:30pm — Accellera luncheon:
- Accellera update given by Shishpal Rawat, Accellera Chair
- Accellera Technical Excellence Award Presentation
- Update on Portable Stimulus Working Group
- Tutorial 3: Cut Your Design Time in Half with Higher Abstraction
- Tutorial 4: SystemVerilog-AMS: The Future of Analog/Mixed Signal Modeling
5:00pm -7:00pm — DVCon Expo and Booth Crawl
The industry's premier conference and exhibition on functional design and verification of electronic systems, DVCon U.S. offers attendees a comprehensive, information-packed 4-day technical program beginning on February 29-March 3 at the DoubleTree Hotel, San Jose, Calif.
The conference will offer attendees a highly technical selection of 36 papers, 12 tutorials and approximately 35 poster presentations. The keynote, “Design Verification Challenges: Past, Present, and Future,” will be given by Wally Rhines, chairman and CEO of Mentor Graphics.
Networking is a hallmark of DVCon U.S., and the Expo offers excellent opportunities for meeting with peers, as well as face-to-face meetings with experts from exhibiting companies, on Monday from 5:00pm-7:00pm and Tuesday and Wednesday from 2:30pm-6:00pm.
The complete set of DVCon U.S. 2015 tutorials is available here.
DVCon Europe will be held October 19-20, 2016 at the Holiday Inn Munich City Centre in Munich. Book your travel early to take advantage of discounted hotel room rates. The 2016 Call for Papers and Call for Tutorials are now live!
DVCon attendees have the opportunity to take part in the many informal, but often intense, technical discussions that pop up around the conference venue among 500+ design and verification engineers and engineering managers. This networking opportunity among peers is possibly the greatest benefit to DVCon attendees. DVCon attendees also have access to the vendors of advanced design and verification tools, IP/VIP and services who exhibit at the conference.
The Accellera SystemC Verification Working Group (VWG) is making available an early UVM-SystemC Language Reference Manual (LRM) accompanied by a Proof-of-Concept (PoC) implementation for public review. The purpose of this public review is to obtain feedback on the LRM and PoC library. The working group is looking for discrepancies versus the standard, and simple install/documentation issues against the supported platforms. It is also interested in patches for expanding the official platform list. The draft document can be found here.
2016 Global Sponsors
Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.
Copyright 2016 Accellera Systems Initiative