Phil Moorby Honored at DVCon U.S.
Moorby Honored Posthumously with 2023 Technical Excellence Award
Phil Moorby, the inventor of the Verilog Hardware Description Language (HDL) who passed away in September 2022, was honored posthumously with the Accellera 2023 Technical Excellence Award during a luncheon at DVCon U.S. Mr. Moorby invented Verilog HDL in 1984 and developed the industry standard simulator Verilog-XL. His continued work to improve Verilog led to the SystemVerilog standard. He has been honored with many awards for his work, including the prestigious Phil Kaufman Award in 2005. He also received a Fellow Award from the Computer History Museum in 2016 for his invention and the promotion of Verilog HDL.
For the full press release visit here
For more information on Accellera’s Technical Excellence Award, including past recipients, visit here.
Accellera Establishes Stanley J. Krolikoski Scholarship for Electrical Engineering and Computer Science Students
Stan is a long time friend and colleague of Accellera and was a Director and served on the Board for 22 years. He retired from Cadence Design Systems in 2021 as a Fellow. The $1,500 scholarship will be awarded each year to one undergraduate student. Students can re-apply each year. Applications will be accepted between January 1 and April 30 and the recipient will be notified by June 1st.
For more information, including a list of requirements and an application, visit here.
Accellera Forms Clock Domain Crossing WG
The new Clock Domain Crossing (CDC) Working group will focus on defining a standard CDC collateral specification to ease SoC integration. Currently, SoC teams cannot reuse IP-level CDC collateral in the SoC environment if both teams use different CDC verification tools, causing a time-consuming CDC verification problem. The CDC Working Group will address the current incompatibility, which will help to greatly improve productivity.
Find out more about the CDC Working Group >
DVCon Japan 2023
DVCon Taiwan 2023
DVCon India 2023
DVCon China 2023
Subscribe to our mailing list:
- Article: Speeding the Path to Industry Standardization with Accellera
- Article: Accellera Update at DVCon 2023
- February newsletter now available
- Article: What’s New in the 2022 IEEE IP-XACT Standard? Big Reveals from the Chair
- Podcast: The International Impact of Accellera’s Work
- Article: Weighing Chip-Design-Verification Challenges for MedTech
- Article: Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development
- Accellera Systems Initiative Posthumously Honors Phil Moorby with 2023 Technical Excellence Award
March 1st, 2023
- Accellera Announces the Formation of the Clock Domain Crossing Working Group
January 17th, 2023
- Accellera’s Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization
January 17th, 2023
- Where Is the Functional Safety Standard and Why Adopt It?
- Portable Stimulus: What's Coming in 2.0 and What it Means For You
- Getting to Know Accellera’s Emerging Hardware Security Standard: Security Annotation for Electronic Design Integration
- UVM-AMS: A UVM-Based Analog Verification Standard
Tweets by Accellera (@accellera)
Login / Register
Access to some downloads and areas within the site is restricted. We encourage you to register and log in.
- Already Registered? Log in!
- Register for Access as a Member Employee
- Site help
- Reset username/password