RE: [sv-ec] Testbench examples ...#1step

Cliff,

Regarding #1step vs. preponed: 
I agree there is no functional difference.  Do you know whether there is
a performance difference?  If a simulator does not treat #1step as
occurring in the preponed region, does that imply it must evaluate a
whole new time step that would not have been needed if the #1step was
not present?

Mark

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Clifford E. Cummings
Sent: Thursday, November 02, 2006 9:49 PM
To: sv-ec@eda.org
Subject: [sv-ec] Testbench examples for the face-to-face meeting

Hi, All -

Per my action Item from Mehdi, I have put some slides with notes out on
the following web page:
www.sunburst-design.com/SVNotes

Feel free to download and review before Monday's meeting. It shows some
testbench methodologies and techniques that are worth considering as we
clarify clocking and program blocks.

I will also be interested in talking about:
- bi-directional port on DUTs and programs (timing and assignment
techniques compared to Verilog - I will try to create some example notes
and also put them on the SVNotes web page).
- possibly adding nonblocking assignments to continuous assignments(?)
- the last paragraph of the clocking block section and the whole notion
of using procedural blocks to make continuous-resolved assignments (very
strange - I missed this when the section was being created).
- time-0 clock and reset strategies (I will tey to add notes to the
SVNotes web page).

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog,
SystemVerilog, Synthesis and Verification Training