RE: [sv-ec] Testbench examples ...#1step

Hi, Mark -

I do not know if there is a performance difference between sampling 
in the previous postponed versus sampling in the current preponed 
regions. Perhaps vendors would like to express thoughts or 
experiences on this (?)

Contrary to your example, I wonder if sampling in the previous 
postponed region is better for performance. From my perspective, once 
a clocking edge is detected, before making any updates in the current 
time slot, a tool could just look at the current values of the 
signals that needed to be sampled (no need to re-sample in the 
preponed region). These values would be equivalent to values sampled 
in the previous postponed region. On the other hand, if a tool had to 
sample in the preponed region, the tool might have to execute the 
sampling action, which might force additional simulator activity.

Just my thoughts. Since I am not an implementor, I really do know how 
(or where) the vendors are doing this.

Regards - Cliff

At 06:33 AM 11/3/2006, Mark Strickland \(mastrick\) wrote:
>Cliff,
>
>Regarding #1step vs. preponed:
>I agree there is no functional difference.  Do you know whether there is
>a performance difference?  If a simulator does not treat #1step as
>occurring in the preponed region, does that imply it must evaluate a
>whole new time step that would not have been needed if the #1step was
>not present?
>
>Mark

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
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