RE: [sv-ec] Testbench examples ...#1step

From: Steven Sharp <sharp_at_.....>
Date: Fri Nov 03 2006 - 10:55:17 PST
As I have pointed out before, #1step will not work the way people
seem to think it will.

SystemVerilog defines 1step (or 2step or any other time literal) to
be a real number.  The "step" suffix means that it is scaled to the
finest precision in the design.  That defines the real number that
1step represents.

Verilog defines the semantics of #<number>, which includes rounding
to the local time precision.  If the local time precision is coarser
than the finest precision in the design, then the real number that
is represented by 1step will be rounded to zero.  So #1step will be
equivalent to #0.  It will not delay by the finest precision in the
design as people seem to think it will.

People can continue to ignore inconvenient facts, but that doesn't
change them.

Steven Sharp
sharp@cadence.com
Received on Fri Nov 3 10:55:21 2006

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