RE: [sv-ec] Testbench examples ...#1step

Jonathan,

The intent for 1step was definitely to make it behave as a special case
so that regardless of any local precision it would sample the value
present in the postponed region of the previous time-slot, which is the
same as the value present in the current preponed region. Current in
this case means the time-slot in which the corresponding clock triggers.
I believe this is consistent with your second definition.

	Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Jonathan Bromley
Sent: Saturday, November 04, 2006 1:55 PM
To: stuart@sutherland-hdl.com; sv-ec@eda-stds.org
Subject: RE: [sv-ec] Testbench examples ...#1step

Stu,

I offered two suggestions:
(1) redefine "input #0" to mean "input sampling in the current
    preponed region", which is a drastic change from the 
    current LRM as it removes the existing input #0 
    functionality;
(2) redefine "input #1step" to mean "input sampling in
    the current preponed region", which is probably less
    disruptive but means that it no longer makes much sense
    to use "step" as a time unit of general usefulness.

My personal preference is strongly for (1), but I fear
it will break too much existing code to be acceptable.

I wasn't entirely clear from your post which you were 
supporting - your first sentence describes my (1), but
your later discussion seems to be talking about (2).

> I would further suggest that we enhance the timeprecision 
> statement to allow something like:
>   timeunit 1ns;
>   timeprecision 1step;

That sounds useful but it has some repercussions
for implementations; decisions about the rounding of time
values would need to be postponed to elaboration time.
-- 
Jonathan Bromley, Consultant

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