Arturo, > The intent for 1step was definitely to make it behave as a > special case > so that regardless of any local precision it would sample the value > present in the postponed region of the previous time-slot, That was my original (albeit rather vague) understanding too. If this is so, then surely it makes no sense whatever for "step" to be a time unit. It is also of very doubtful value to do stuff like stmt1; #1step stmt2; because, just as you find if you try to wait for the event "sys.any" in 'e', the delay thus achieved is a hostage to fortune - its meaning can be affected by parts of the simulation that are quite unrelated to the code that concerns you. As I have pointed out, all current tools seem to handle #1step in the special way you describe, so it makes good sense to formalize that understanding in the LRM. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Received on Sun Nov 5 09:01:48 2006
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