RE: [sv-ec] Testbench examples ...#1step

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Sun Nov 05 2006 - 09:01:39 PST
Arturo,

> The intent for 1step was definitely to make it behave as a 
> special case
> so that regardless of any local precision it would sample the value
> present in the postponed region of the previous time-slot, 

That was my original (albeit rather vague) understanding too.

If this is so, then surely it makes no sense whatever for
"step" to be a time unit.  It is also of very doubtful value
to do stuff like

  stmt1;
  #1step stmt2;

because, just as you find if you try to wait for the 
event "sys.any" in 'e', the delay thus achieved is
a hostage to fortune - its meaning can be affected
by parts of the simulation that are quite unrelated
to the code that concerns you.

As I have pointed out, all current tools seem to handle 
#1step in the special way you describe, so it makes good
sense to formalize that understanding in the LRM.
-- 
Jonathan Bromley, Consultant

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Received on Sun Nov 5 09:01:48 2006

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