RE: Revisions to 1064.1 Section 4, Semantics

Muzaffer Kal (muzaffer@smixedsignal.com)
Thu, 30 Jul 1998 15:34:15 -0700

I think this is the crucial argument for functions and tasks. We have no
other means of doing this (simple code re-use) in Verilog (if I am mistaken
I am willing to be educated but regular macros are not good enough). I think
we need this functionality in the synthesizable subset.

Muzaffer

> But even more simply, you can think of functions and
> tasks in even their most primitive forms as macros with
> parameters. The
> moment the actual parameters are different for different calls of the
> function, the synthesis tool will not be able to unite them.
>
> The synthesis tool does not look at a function or task as a chunk
> of logic which appears
> only once in the circuit, but as a logical function which
> reappears everywhere it is instantiated.