At the recent face-to-face meeting we discussed pragmas. One of
the issues was a means of communicating to a synthesis tool that
it should map directly to a multiplexer. As such I have am proposing
// rtl_map_to_mux
which can be associated with a case or if statement.
The problem I see with this is that it could excalate, for example,
why not hae a pragma for mapping onto a counter.
Please send in and feedback. When I send out email to this reflector
I will include at the bottom a full list of proposed prgmas as they
exist at that point in time. Currently this is as follows.
Doug Smith
Verilog IEEE 1364.1 - proposed pragmas
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The following pragmas are being proposed for the standard:
1. Conditional compilation pragmas
// rtl_synthesis off
// rtl_synthesis on
2. Case decoding pragmas
// rtl_full_case
// communicates to the synthesis tool case choices are exhaustive.
// rtl_parallel_case
// communicates to the synthesis tool case choices are mutually
exclusive.
3. Mapping to a multiplexer
// map_to_mux
// communicates to the synthesis tool to map directly to a
multiplexer
// and shall apply to case and if statements.