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DVCon India: A Growing Event

by Gabe Moretti
September 2, 2015

Launched with great success last year, DVCon India is back this year with an expanded program.  This year the conference will be held in Bangalore on September 10 and 11 at the Leela Palace.  Sponsored by Accellera Systems Initiative, the conference will provide opportunities for professional growth, networking, and familiarization with the standardization work that goes on in Accellera.  The success of the first DVCon India has resulted in moving the conference to a larger venue, increasing both the number of technical sessions and tutorials as well as increasing the exhibit space.  The exhibit booths will be open both days of the conference in order to offer flexibility to attendees as they plan their daily schedules.

India has had a relatively long presence in EDA.  I remember that Intergraph/Veribest had a verification laboratory in Hyderabad in 1992, the year I joined the company.  EDA capabilities have grown significantly in India with all major EDA companies having a presence there.  Indian companies are active not only in verification, but also in design, both at the ASIC level and at the IP level.  Some of the most financially successful Indian EDA companies are active in the service sector, providing expert manpower to system companies.

This year DVCon India will be celebrating the 10-year anniversary of SystemVerilog.  On the first day of the conference there will be a gala dinner to celebrate the anniversary as well as the release of Universal Verification Methodology (UVM) 1.2 to the IEEE P1800.2 working group for development and ongoing maintenance as an IEEE standard.  Both standards are examples of Accellera’s leadership in EDA.

SystemVerilog is both a design and a verification language and thus improves the communication between designers and verification engineers, reducing the project schedule.  UVM, a powerful methodology in its own right, increases the power of SystemVerilog and allows engineers to develop portable verification components. 

The technical program is divided into two tracks.  One covers Design and Verification (DV) with a variety of topics including SystemVerilog and UVM, low power, portable stimulus, and more, while the other focuses on electronic system level (ESL) issues and provides a vehicle to discuss SystemC and TLM topics among others. 

Two keynote speeches, one by Harry Foster of Mentor Graphics and one by Vinay Shenoy of Infineon Technology India, will kick off the conference.  After a break, the program divides into the two tracks —the ESL track will offer another keynote speech and an invited speech, while the DV track will offer a keynote speech by Nick Heaton of Cadence followed by a panel discussion on IoT verification.

The entire afternoon of the first day is dedicated to tutorials, with six covering SystemVerilog and UVM topics and four covering ESL topics.  The sequence of ESL tutorials will be broken in half with invited talks given by Vladimir Ivanov of LG Electronics and Pankaj Singh of Infineon.  Dr. Sacha Loitz of Continental will speak in the evening.  The DV track will hold another panel discussion with the topic “Supporting the Evolving Verification Flow.”

The 9:30 start of the second day program allows those who took the previous evening’s celebration really seriously to have recovered enough to appreciate the scheduled presentations.  A keynote speech by Manoj Gandhi of Synopsys and an invited keynote by Atul Bhatia, an entrepreneur, will set the tone for the rest of the day.  After a break, the ESL track will continue with panels and papers.  The high number of papers received and accepted by the Program Committee forced the ESL track to be split into two parallel tracks in the afternoon.  The DV track, for the same reason, offers three parallel tracks for the entire day.  The first DV track is dedicated to SystemVerilog and UVM topics, while the second covers a list of technical issues including emulation, FPGA, and acceleration (morning) and  Formal techniques, clock tree design, and AMS (afternoon). The third track focuses on portable stimulus and coverage in the morning, while in the afternoon it deals with stimulus generation in SoC designs, VHDL, Verilog AMS, and static timing analysis.

I think attendees may at times have a hard time deciding what to attend, given that a tour of the exhibit floor will also be of significant interest.  What immediately jumped to my attention while perusing the technical program is the impressive number of Indian presenters in all of the tracks.  This, if there were still a need for justification, is a clear example of the growth of EDA in India.  Accellera can take pride in being the international consortium that has fostered such growth, organizing Indian events such as a SystemC Users Group get together as well as supporting both Verilog and VHDL modeling languages.