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New Video Tutorial – UVM: Ready, Set, Deploy!

It’s been six months since Accellera and the Open SystemC Initiative joined forces to become Accellera Systems Initiative. In that time, we have achieved several milestones in developing standards that address the real needs of system and semiconductor designers.

The Universal Verification Methodology (UVM) standard continues to gain adoption across the verification community. Presented by expert verification methodology architects and engineers at DVCon 2012, the eight-part video tutorial is available at no cost to users and provides an introduction to key UVM concepts and best practices.

See us at the Design Automation Conference, June 4-7 in San Francisco! We will be hosting several events at this year's DAC including a luncheon on the Unified Coverage Interoperability Standard (UCIS), NASCUG meeting, and special birds-of-a-feather sessions. Events are no charge with advance registration required. Read the latest article on UCIS featured in our newsletter.

DAC 2012

June 6 | San Francisco, CA

Hosted Luncheon and UCIS Technical Presentation
Birds-of-a-Feather Meetings
NASCUG XVIII

Find out more >

SystemC Japan

July 6 | Yokohama, Japan

DVCon 2013

Call for abstracts >

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Recent Happenings

• Now accepting nominations for our first annual Leadership Award.

• May newsletter now available.

• John Aynsley receives the 2012 Technical Excellence Award.

• IEEE 1666-2011 Now Available for Free Download courtesy of Accellera Systems Initiative.

• Open Verification Library (OVL) 2.6 release is now available for download.

• UVM 1.1 is now available for download.

OSCI and Accellera Unite

The new organization will leverage the complementary efforts of both groups to create more comprehensive standards.

• Welcome from the Chair

• Read what Accellera Systems Initiative members and others are saying

• Frequently Asked Questions

News

Featured Quote

"With the release of the SystemC AMS 2.0 draft standard, we finally fulfill a longstanding and demanding requirement of the automotive industry to dynamically change time steps and data rates during simulation," said Martin Barnasconi, Chairman of the SystemC AMS Working Group. "I'm very pleased to be achieving this milestone, exactly 10 years after the formation of the study group that started developing AMS extensions to SystemC. I invite the SystemC community to participate in this public review, which will definitely boost the adoption of mixed-signal system-level design methodologies based on SystemC and SystemC AMS in industries such as automotive and semiconductors."... More »

Other News From the Industry

IEEE APPROVES REVISED IEEE 1666™ "SYSTEMC LANGUAGE" STANDARD FOR ELECTRONIC SYSTEM-LEVEL DESIGN, ADDING SUPPORT FOR TRANSACTION-LEVEL MODELING

New version to enable higher level, more efficient design of complex integrated circuits and system-on-chips

PISCATAWAY, N.J., USA, 10 November 2011 – IEEE, the world's largest professional association advancing technology for humanity, today announced that the IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666™ "Standard SystemC Language Reference Manual," which specifies SystemC, the high-level design language used in the design and development of electronic systems. The new version of IEEE 1666 encompasses many enhancements, notably the support for transaction-level modeling (TLM), a critical approach to enable higher level and more efficient design of complex integrated circuits (ICs) and system-on-chips (SoCs). More »