Download Verilog-AMS
The Verilog-AMS Hardware Description Language (HDL) language defines a behavioral language for analog and mixed-signal systems. It is derived from the IEEE 1364 Verilog HDL specification.
Verilog-AMS is developed by the Verilog-AMS Technical Subcommittee.
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Current Release
| Item | Filename | Details | Size | Date Modified |
| VAMS 2.3.1 | VAMS-LRM-2-3-1.pdf | Verilog-AMS Language Reference Manual, Release 2.3.1 | 3,730,608 | 2009-06 |