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The Verilog-AMS Hardware Description Language (HDL) language defines a behavioral language for analog and mixed-signal systems. It is derived from the IEEE 1364 Verilog HDL specification.

Verilog-AMS is developed by the Verilog-AMS Technical Subcommittee.

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Current Release

Item Filename Details Size Date Modified
VAMS 2.3.1 VAMS-LRM-2-3-1.pdf Verilog-AMS Language Reference Manual, Release 2.3.1 3,730,608 2009-06
Driver Access Macros driver_access.vams Header file for standard driver access macros 1,535 2013-07
Constants constants.vams Header file for standard constants  1,885  2013-07
Disciplines disciplines.vams Header file for standard discipline definitions  5,788  2013-07