> Sections 4.2.1.1 and 4.2.1.2 in the draft refer to the
> verilog syntax for representing edge-sensitive logic:
>
> always @(posedge clock)
> or always @(negedge clock)
>
> and of course either can have an asynchronous reset
> term (although the comment in the last part of the
> example on page 13 says "synchronous reset" which
> I think is wrong, no?).
>
> But, during recent a discussion on comp.lang.verilog
> it emerged that the Synplicity tool will synthesize
> RTL where the @(posedge clock) is *within* the always
> block. I've given the example at the end of this mail,
> but my question is, "is this desirable?".
>
> design_compiler from synopsys refuses to accept
> such a construct, and because that is the only
> tool I've used I've come to feel that @(posedge ...)
> belongs only in the sensitivity list of an always
> block. In that, both Synopsys and I seem to be in
> agreement with the authors of the draft standard.
>
> Thoughts?
>
> regards,
> Tommy
>
Several quick comments.1) This would be a "synchronous reset". For it
to be
asynchronous you would need reset defined in the always
sensitivity list. Hence, "always @(posedge clk)" will only
evaluate the reset signal at the positive edge of clk.
"always @(posedge clk or reset)" will cause evaluation at
the posedge of clock or any change in the reset signal.
2) Last I checked "Tasks" are not synthesizable constructs.
Best of luck
-jim
> /* Here's the example */
>
> module test(
> reset, clock,
> req1, req2,
> ack1, ack2
> );
> input reset;
> input clock;
> output req1;
> output req2;
> input ack1;
> input ack2;
>
> reg req1;
> reg req2;
>
> reg [0:2] state;
> `define DO_FIRST 3'b001
> `define DO_SECOND 3'b010
> `define IDLE 3'b100
>
>
> always @(posedge clock)
> begin
> if (reset)
> begin
> req1=0;
> req2=0;
> end
> else begin
> case (state)
> `DO_FIRST:
> begin
> handshake1;
> state=`DO_SECOND;
> end
> `DO_SECOND:
> begin
> handshake2;
> state=`IDLE;
> end
> `IDLE:
> state=`DO_FIRST;
> default:
> state='bx;
> endcase
> end
> end
>
> task handshake1;
> begin
> req1=1;
> while (ack1==0 && reset==0)
> @(posedge clock);
> req1=0;
> while (ack1==1 && reset==0)
> @(posedge clock);
> end
> endtask // handshake1
>
>
> task handshake2;
> begin
> req2=1;
> while (ack2==0 && reset==0)
> @(posedge clock);
> req2=0;
> while (ack2==1 && reset==0)
> @(posedge clock);
> end
> endtask // handshake2
>
> endmodule // test
>
> /* End of example */