Subject: Re: Verilog-AMS - Issue 15: `include
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Jul 09 2002 - 12:52:09 PDT
Mac writes:
:Simon Davidmann writes:
: > [1 <text/plain; us-ascii (7bit)>]
: >
: > In C the methodology is all about using header files - and more so
: > with C++. In my experience, in Verilog this is not the case
: >
:I disagree! Good Verilog design strategy very definiatly uses include
:files.
You two are arguing two different points - experience (history) vs.
methodology.
I agree with Simon. Verilog designers say, 'what's an include file?
It sounds evil!"
Synopsys design compiler is anti include files. They require you to
enable
preprocessing to even recognize include files (via set hdlin_enable_vpp
TRUE).
They do not support defines very well either, requiring to use a define
if
set (and produce an error if the define is not used in the file.)
I agree with Mac, that include files are part of a good methodology.
You share common information rather than duplicate it and have the wrong
value.
Back to the request, I do not see the value of supporting <>. Tools are
free
to define the include file search path to what they desire. We already
support
the +incdir+<dir>[+<dir>] to extend the search paths.
The only (bad) thing that <> allows is to have a system include file
matching
the name of a user include file. This would be a bad, dangerous
practice.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 70574
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