Subject: Re: Verilog-AMS - Issue 15: `include
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Jul 09 2002 - 10:21:08 PDT
> From simond@co-design.com Tue Jul 9 09:32:44 2002
>
> In C the methodology is all about using header files - and more so with C++
>
> in my experience, in Verilog this is not the case
>
> what are 'system include' files - in a verilog world what would they be for?
>
> Simon
Verilog-A[MS] has header files defining math constants (e.g. `PI) and
disciplines (e.g. "electrical" which lets you use the accesss function
V(n) instead of potential(n)). Other header files will probably be added
later which will indicate vendor-specific capability (e.g. analog
primitive declarations). These header files are included optionally by
the user and may be overridden by the user, the intention of the <>
syntax is that it will look only in the system headers for a file and
not in the user defined header directory list. E.g.
`include <spice.h> // include only from system headers
`include "spice.h" // Use my version if present and fall-back to system
I expect SystemVerilog will also accumulate similar standard header files
for common external definitions and implementation dependent features as
time goes on.
BTW, would the CPP syntax '#include ...' clash with SystemVerilog? If not
could we add it as an alternate syntax? - E.g. lines begining with "`"
are treated the same as lines beginning "#".
Kev.
> At 05:10 PM 7/8/2002, Kevin Cameron x3251 wrote:
>
> >http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0015/index.html
> >
> >I was asked to run this by the SystemVerilog committee.
> >
> >Does anyone object to using C-like angle brackets for system include
> >files in a future SystemVerilog (assuming we combine it with Verilog-AMS
> >- version 4.X! )?
> >
> >Verilog-A has various bundled header files for constants and disciplines
> >we would like to identify as different from user files of the same name.
> >
> >Feedback appreciated,
> >Kev.
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