Subject: Re: Verilog-AMS - Issue 15: `include
From: Shalom.Bresticker@motorola.com
Date: Tue Jul 09 2002 - 11:45:39 PDT
I think adding #include to SV would not be a good idea.
Many use CPP as a preprocessor to Verilog.
I imagine it will occur with SV too.
Shalom
On Tue, 9 Jul 2002, Kevin Cameron x3251 wrote:
> BTW, would the CPP syntax '#include ...' clash with SystemVerilog? If not
> could we add it as an alternate syntax? - E.g. lines begining with "`"
> are treated the same as lines beginning "#".
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