Subject: Re: Verilog-AMS - Issue 15: `include
From: Steven Sharp (sharp@cadence.com)
Date: Tue Jul 09 2002 - 12:09:30 PDT
>BTW, would the CPP syntax '#include ...' clash with SystemVerilog? If not
>could we add it as an alternate syntax? - E.g. lines begining with "`"
>are treated the same as lines beginning "#".
Presumably Verilog used ` instead of # to avoid parsing problems and/or
confusion with #delay syntax. The decision has already been made on the
syntax. I don't see any reason to re-visit it. Nor is it a good idea to
start adding multiple syntaxes for everything in the language.
Steven Sharp
sharp@cadence.com
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